综合时latch如何配置

bosscat87

latch是电平触发，用使能G端的下降沿对数据D端进行setup和hold检查，请问综合时如何配置使能端才能让综合工具自动优化时序，或者如何设置约束效果好？

九鲤湖

同求，顶一个

xiaoyisimonguo

回复 1# bosscat87


   I thought a lot of places would not allow latches in post-synthesis netlist.Just wondering if it is common practice to avoid latches

chenfengrugao

回复 1# bosscat87


    1. latch的时钟端create_clock
    2. set_clock_transition, set_clock_uncertainty -setup , set_clock_uncertainty -hold
    3. set_max_time_borrow

跟普通的clk没太大差别。