Vivado下实例化HDL代码

Zrh

刚开始用Vivado，发现找不到ISE中生成实例化模板的选型了，只能自己写。在网上搜索了一下，几乎没有给出答案，最终在Xilinx官网找到了解决方案：

Install the Designutils app in the Tcl Appstore (Tools -> Xilinx Tcl Store) if it has not been previously installed.


The module should be set as top-level.

When it is elaborated or synthesized:

• Run "xilinx::designutils::write_template" to create a stub, template or testbench.
• Run "xilinx::designutils::write_template -usage" for usage information.

详见：AR#58023。

官网给出的是Vivado 2014.1，经测试，之后版本都可用，只是不方便的是使用时要把被例化模块设置为顶层模块。

ibubapa

回复 1# Zrh


    thanks for sharing

ayamitek

回复 2# ibubapa


    thanks for sharing

ahmad.reda2019

thanks alot.
very helpful