关于create_generate_clock

xiaowang8900

回复 6# masaka_xlw

   不过ICG应该是可以穿过去的吧？

sdlyyuxi

回复 9# xiaowang8900


   就像你回复我上个条目说的那样， set_propagate_clock 在post layout才用。那么在ideal network阶段，如果你想要模拟network latency，那只能一段段的标上。我试了下，如果自己标了network latency, 又设了propagate, 标了的值就无效了。两者互斥，很合理。     毕竟你已经设了 不允许propagate.
    By default, the tool assumes ideal clocking, which means clocks have a specified network latency (from the set_clock_latency command) or zero network latency by default. Propagated clock network latency (from the set_propagated_clock command) is normally used after layout and final clock tree generation.
     Specifying the ideal clock network latency provides an estimate of the clock tree delay for before layout.

xiaowang8900

回复 12# sdlyyuxi


   恩，谢谢啦

masaka_xlw

回复 10# xiaowang8900
正常情况下ICG在任何tech process下都是能被时钟穿过的。感觉有点像时钟树在前仿和后仿中，工具如何解释的问题。
一般后仿直接就propagate了，延迟参数直接从后端过来。前仿真往往都是ideal的，除非强行force delay。。