小白首次搭建环境

johnakeke

回复 8# zzj0329


   Note: This design requires that the GRLIB_SIMULATOR variable iscorrectly set. Please refer to the documentation in doc/grlib.pdf for
additional information.


Note: The Vivado flow and parts of this design are still
experimental. Currently the design configuration should be left as-is.


Note: You must have Vivado 2014.4.1 in your path for the make targets to work.


The XILINX_VIVADO variable must be exported for the mig_7series target
to work correctly: export XILINX_VIVADO


Simulation and synthesis
------------------------


The design uses the Xilinx MIG memory interface with an AHB-2.0
interface and Xilinx SGMII PHY Interface. The MIG or the SGMII PHY
source code cannot be distributed due to the prohibitive Xilinx
license, so the MIG and/or the SGMII must be re-generated with
Vivado before simulation and synthesis can be done.


Xilinx MIG and SGMII interface will automatically be generated when
Vivado is launched  


To simulate using XSIM and run systest.c on the Leon design using the memory
controller from Xilinx use the make targets:


  make soft
  make vivado-launch


To simulate using Modelsim/Aldec and run systest.c on the Leon design using
the memory controller from Xilinx use the make targets:


  make map_xilinx_7series_lib
  make sim
  make mig_7series
  make sgmii_7series
  make sim-launch


To simulate using the Aldec Riviera WS flow use the following make targets:


  make riviera_ws               # creates riviera workspace
  make map_xilinx_7series_lib   # compiles and maps xilinx sim libs
  make mig_7series              # generates MIG IP and adds to riviera project
  make sgmii_7series            # same for SGMII adapter
  make riviera                  # compile full project
  make riviera-launch           # launch simulation


To synthesize the design, do


  make vivado


and then use iMPACT programming tool:


  make ise-prog-fpga


to program the FPGA.


//大概给了这么一个说明，但是就是跑不通

doukai

回复 1# johnakeke


   你好，最近也在搞leon3的xilinx FPGA移植，跑不通，软件下载不进去，你的搞好了吗？

weiqingchen

加油加油

ldl8023

回复 12# doukai


   你好，最近也在搞leon3的FPGA移植，你的搞好了吗？方便留个联系方式交流下吗

xtwl_tpcl

FPGA开发 V7的话 Vivado工具就可以了
用虚拟机对性能有影响，要么都在linux，要么都在windows下

745579593

建个工程 代码放进去 fpga选好，建个ucf 管脚对着电路图 设好，生成bit file ，烧到fpga里

怎么个景

回复 16# 745579593
你好，你搞过这个Leon3在xilinx-vc-707上么？能否请教下，跑仿真跑不过，提示 library unsim not found，但是以及知行make install-unsim命令了；我用的软件是，Linux下的ISE 14.7，仿真用的modelsim。

rayslike

777777777777777

江山无限辉

没有移植过，帮顶

xu_xu

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