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工程利用ISE自带的FIFO核将32位的并行数据经过缓存以单bit输出，读写时钟相同，首先将32位数据经过FIFO1变成8位输出，再将8位数据经过FIFO2变成1位输出，对程序仿真结果显示正确，但是下载到板子测试的时候，却得不到输出数据，求大神帮忙看看是否是代码的问题呢？多谢啦
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use ieee.std_logic_arith.all;
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity transmit is
PORT(
clk_100M : in std_logic;
-- clk_100M : in std_logic;
nrst : in std_logic;
fifo_data_in : in std_logic_vector(31 downto 0);
empty_1 : in std_logic;
reden : out std_logic;
fifo_data_out : out std_logic_vector(0 downto 0)
);
end transmit;
architecture Behavioral of transmit is
COMPONENT fifo1
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo2
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
signal fifo1_data_in_1 : std_logic_vector(31 downto 0);
signal fifo1_data_in_2 : std_logic_vector(31 downto 0);
signal empty_2 : std_logic;
signal reden_1 : std_logic;
signal fifo1_data_out_1 : std_logic_vector(7 downto 0);
signal fifo2_data_out_2 : std_logic_vector(0 downto 0);
signal reden_1_d1 : std_logic;
--signal clk_100M : std_logic;
--signal clk_40M : std_logic;
----fifo1
signal wr_en_d1 : std_logic;
signal wr_en_d1_1 : std_logic;
signal wr_en_d1_2 : std_logic;
signal rd_en_d1 : std_logic;
signal full_d1 : std_logic;
signal empty_d1 : std_logic;
----fifo2
signal wr_en_d2 : std_logic;
signal rd_en_d2 : std_logic;
signal full_d2 : std_logic;
signal empty_d2 : std_logic;
begin
fifo_data_out<=fifo2_data_out_2;
process(clk_100M)
begin
if(clk_100M'event and clk_100M='1') then
fifo1_data_in_1<=fifo1_data_in_2;
fifo1_data_in_2<=fifo_data_in;
reden_1_d1<=reden_1;
end if;
end process;
----fifo1
process(nrst,clk_100M,reden_1,empty_2)
begin
if (nrst='0') then
wr_en_d1 <='0';
wr_en_d1_1 <='0';
wr_en_d1_2 <='0';
-- rd_en_d1 <='0';
-- rd_en_d1 <='0';
elsif (clk_100M'event and clk_100M='1') then
empty_2<=empty_1;
wr_en_d1_1<= wr_en_d1;
if (empty_2='0' and full_d1='0') then
wr_en_d1 <='1';
reden_1 <='1';
else
wr_en_d1 <='0';
reden_1 <='0';
end if;
end if;
end process;
wr_en_d1_2 <= wr_en_d1;
reden <= reden_1_d1;
process(nrst,clk_100M,empty_d1)
begin
if (nrst='0') then
wr_en_d2<='0';
elsif (clk_100M'event and clk_100M='1') then
if (empty_d1='0' and full_d2='0') then
wr_en_d2<='1';
rd_en_d1<='1';
else
wr_en_d2<='0';
rd_en_d1<='0';
end if;
end if;
end process;
process(clk_100M,empty_d2)
begin
if (clk_100M'event and clk_100M='1') then
if (empty_d2='0' ) then
rd_en_d2<='1';
else
rd_en_d2<='0';
end if;
end if;
end process;
fifo_save : fifo1
PORT MAP (
rst => nrst,
wr_clk => clk_100M,
rd_clk => clk_100M,
din => fifo1_data_in_1,
wr_en => wr_en_d1,
rd_en => rd_en_d1,
dout => fifo1_data_out_1,
full => full_d1,
empty => empty_d1
);
fifo_trans : fifo2
PORT MAP (
rst => nrst,
wr_clk => clk_100M,
rd_clk => clk_100M,
din => fifo1_data_out_1,
wr_en => wr_en_d2,
rd_en => rd_en_d2,
dout =>fifo2_data_out_2,
full => full_d2,
empty => empty_d2
);
end Behavioral; |
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发表于 2016-12-23 12:55:19
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