实例化出现cannot be assigned more than one value求助

leeslyy · 发表于 2016-6-22 10:48:53

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[code]module txmit(
input wire sys_clk , //system clock;
input wire sys_rst_n , //system reset, low is active
output reg uart_txd,
input wire [7:0]data_in
);

reg [7:0] buff ;

reg txd ;
reg [19:0] counter ;

reg [23:0] delay_count ;

//assign LED = buff;
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)begin // 鍒濆?鍖buff, 澶嶄綅鏃跺叏閮ㄦ竻闆
buff <= 8'b0;
end
else begin
buff <= data_in;
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if ( sys_rst_n == 1'b0)begin
delay_count <= 24'b0;
end
else if (delay_count <= 24'd50000000 )begin
delay_count <= delay_count+ 24'b1;
end
else begin
delay_count <= 24'b0;
end
end
always @(posedge sys_clk or negedge sys_rst_n ) begin
if ( sys_rst_n ==1'b0 )begin
counter <= 20'b0;
end
else if (delay_count == 24'd50000000)begin
//counter 鍦鍦delay_count 璁℃暟鍒DELAY_CNT 鏃跺紑濮嬪彂閫佹暟鎹
counter <= 20'b0;
end
else if (counter <= 57200)begin // 瀹屾垚涓

leeslyy · 发表于 2016-6-22 10:51:18

counter <= counter + 20'b1;
end
end
always @(*) begin
if ((counter > 20'd0) && (counter <= 20'd5200 )) begin// start
txd = 1'b0 ;
end else if ((counter > 20'd5200) && (counter <= 20'd10400)) begin// D0
txd = buff[0] ;
end else if ((counter > 20'd10400) && (counter <= 20'd15600))begin // D1
txd = buff[1] ;
end else if ((counter > 20'd15600) && (counter <= 20'd20800))begin // D2
txd = buff[2] ;
end else if ((counter > 20'd20800) && (counter <= 20'd26000))begin // D3
txd = buff[3] ;
end else if ((counter > 20'd26000) && (counter <= 20'd31200))begin // D4
txd = buff[4] ;
end else if ((counter > 20'd31200) && (counter <= 20'd36400))begin // D5
txd = buff[5] ;
end else if ((counter > 20'd36400) && (counter <= 20'd42000))begin // D6
txd = buff[6] ;
end else if ((counter > 20'd42000) && (counter <= 20'd46800))begin // D7
txd = buff[7] ;
end else if ((counter > 20'd46800) && (counter <= 20'd52000))begin //
txd = 1'b1 ;
end else if ((counter > 20'd52000) && (counter <= 20'd57200))begin //
txd = 1'b1 ;
end else begin
txd = 1'b1 ;
end
end
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
uart_txd <= 1'b1;
else
uart_txd<= txd;
end
Econder u0(.INA(INA),.INB(INB),.LED(data_in));
endmodule