在Verilog中有关模块的例化问题。

甲壳虫 · 发表于 2016-5-10 22:26:19

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x

实在是不知道怎么去例化模块，试着写了，发现有问题，不知道怎么解决？

`timescale 1 ps/ 1 ps
module cordic(clk,rst_n,x,out);
parameter DATA_Length=16; //数据长度
input clk;
input rst_n;
input [DATA_Length-1:0] x; //输入
output [DATA_Length-1:0] out; //输出
//output [DATA_Length-1:0] x_out;
//reg [DATA_Length-1:0] x_out;
reg [DATA_Length-1:0] out;
reg [DATA_Length-1:0] x0,y0,z0;
reg [DATA_Length-1:0] x1,y1,z1;
reg [DATA_Length-1:0] x2,y2,z2;
reg [DATA_Length-1:0] x3,y3,z3;
reg [DATA_Length-1:0] x4,y4,z4;
reg [DATA_Length-1:0] x5,y5,z5;
reg [DATA_Length-1:0] x6,y6,z6;
reg [DATA_Length-1:0] x7,y7,z7;
reg [DATA_Length-1:0] x8,y8,z8;
//初始值赋值//
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
x0<=16'b0000_0000_0000_0000;
y0<=16'b0000_0000_0000_0000;
z0<=16'b0000_0000_0000_0000;
end
else
begin
x0 <= x+(1>>2);
y0 <= x-(1>>2);
z0 <=16'b0000_0000_0000_0000;
end
end
//level 1 流水线一级
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
x1<=16'b0000_0000_0000_0000;
y1<=16'b0000_0000_0000_0000;
z1<=16'b0000_0000_0000_0000;
end
else
if(y0[15]==1'b0)
begin
x1 <= x0 + y0;
y1 <= y0 - x0;
z1 <= z0 + 16'h1000; //45deg
end
else
begin
x1 <= x0 - y0;
y1 <= y0 + x0;
z1 <= z0 - 16'h1000; //45deg
end
end
//level 2 流水线二级
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
x2<=16'h0000 ;
y2<=16'h0000 ;
z2<=16'h0000 ;
end
else
if(y1[15]==1'b0)
begin
x2 <= x1 + {y1[DATA_Length-1],y1[DATA_Length-1:1]};
y2 <= y1 - {x1[DATA_Length-1],x1[DATA_Length-1:1]};
z2 <= z1 + 16'h096c; //26.5651deg
end
else
begin
x2 <= x1 - {y1[DATA_Length-1],y1[DATA_Length-1:1]};
y2 <= y1 + {x1[DATA_Length-1],x1[DATA_Length-1:1]};
z2 <= z1 - 16'h096c; //26.5651deg
end
end
//level 3
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
x3<=16'b0000_0000_0000_0000;
y3<=16'b0000_0000_0000_0000;
z3<=16'b0000_0000_0000_0000;
end
else
if(y2[15]==1'b0)
begin
x3 <= x2 + {{2{y2[DATA_Length-1]}},y2[DATA_Length-1:2]};
y3 <= y2 - {{2{x2[DATA_Length-1]}},x2[DATA_Length-1:2]};
z3 <= z2 + 16'h04fa; //14.0362deg
end
else
begin
x3 <= x2 - {{2{y2[DATA_Length-1]}},y2[DATA_Length-1:2]};
y3 <= y2 + {{2{x2[DATA_Length-1]}},x2[DATA_Length-1:2]};
z3 <= z2 - 16'h04fa; //14.0362deg
end
end
//level 4
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
x4<=16'b0000_0000_0000_0000;
y4<=16'b0000_0000_0000_0000;
z4<=16'b0000_0000_0000_0000;
end
else
if(y3[15]==1'b0)
begin
x4 <= x3 + {{3{y3[DATA_Length-1]}},y3[DATA_Length-1:3]};
y4 <= y3 - {{3{x3[DATA_Length-1]}},x3[DATA_Length-1:3]};
z4 <= z3 + 16'h0288; //7.1250deg
end
else
begin
x4 <= x3 - {{3{y3[DATA_Length-1]}},y3[DATA_Length-1:3]};
y4 <= y3 + {{3{x3[DATA_Length-1]}},x3[DATA_Length-1:3]};
z4 <= z3 - 16'h0288; //7.1250deg
end
end
//level 5
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
x5<=16'b0000_0000_0000_0000;
y5<=16'b0000_0000_0000_0000;
z5<=16'b0000_0000_0000_0000;
end
else
if(y4[15]==1'b0)
begin
x5 <= x4 + {{4{y4[DATA_Length-1]}},y4[DATA_Length-1:4]};
y5 <= y4 - {{4{x4[DATA_Length-1]}},x4[DATA_Length-1:4]};
z5 <= z4 + 16'h0145; // 3.5763 deg
end
else
begin
x5 <= x4 - {{4{y4[DATA_Length-1]}},y4[DATA_Length-1:4]};
y5 <= y4 + {{4{x4[DATA_Length-1]}},x4[DATA_Length-1:4]};
z5 <= z4 - 16'h0145; // 3.5763 deg
end
end
//level 6
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
x6<=16'b0000_0000_0000_0000;
y6<=16'b0000_0000_0000_0000;
z6<=16'b0000_0000_0000_0000;
end
else
if(y5[15]==1'b0)
begin
x6 <= x5 + {{5{y5[DATA_Length-1]}},y5[DATA_Length-1:5]};
y6 <= y5 - {{5{x5[DATA_Length-1]}},x5[DATA_Length-1:5]};
z6 <= z5 + 16'h00a2; //1.7899deg
end
else
begin
x6 <= x5 - {{5{y5[DATA_Length-1]}},y5[DATA_Length-1:5]};
y6 <= y5 + {{5{x5[DATA_Length-1]}},x5[DATA_Length-1:5]};
z6 <= z5 - 16'h00a2; //1.7899deg
end
end
//level 7
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
x7<=16'b0000_0000_0000_0000;
y7<=16'b0000_0000_0000_0000;
z7<=16'b0000_0000_0000_0000;
end
else
if(y6[15]==1'b0)
begin
x7 <= x6 + {{6{y6[DATA_Length-1]}},y6[DATA_Length-1:6]};
y7 <= y6 - {{6{x6[DATA_Length-1]}},x6[DATA_Length-1:6]};
z7 <= z6 + 16'h0051; // 0.8952deg
end
else
begin
x7 <= x6 - {{6{y6[DATA_Length-1]}},y6[DATA_Length-1:6]};
y7 <= y6 + {{6{x6[DATA_Length-1]}},x6[DATA_Length-1:6]};
z7 <= z6 - 16'h0051; // 0.8952deg
end
end
//level 8
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
x8<=16'b0000_0000_0000_0000;
y8<=16'b0000_0000_0000_0000;
z8<=16'b0000_0000_0000_0000;
end
else
if(y7[15]==1'b0)
begin
x8 <= x7 + {{7{y7[DATA_Length-1]}},y7[DATA_Length-1:7]};
y8 <= y7 - {{7{x7[DATA_Length-1]}},x7[DATA_Length-1:7]};
z8 <= z7 + 16'h0028; // 0.4476deg
end
else
begin
x8 <= x7 - {{7{y7[DATA_Length-1]}},y7[DATA_Length-1:7]};
y8 <= y7 + {{7{x7[DATA_Length-1]}},x7[DATA_Length-1:7]};
z8 <= z7 - 16'h0028; // 0.4476deg
end
end
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
out <= 16'b0000_0000_0000_0000;
else
out <= x8;
end
endmodule
module sqrt(clk,rst_n,out,x_out)
input clk,rst_n;
input [15:0] out;
output [15:0] x_out;
reg [15:0] x_out;
cordic U1(
);
always @ (posedge clk or negedge rst_n)
if(!rst_n)
x_out <= 0;
else
x_out <= out+(out>>3)+(out>>4)+(out>>6)+(out>>8);

复制代码

希望可以帮忙一下。谢谢。

huster · 发表于 2016-5-11 08:38:45

端口都不连上去你怎么例化的？我晕了

haimo · 发表于 2016-5-11 09:18:38

cordic U1(.clk(clk), .rst_n(rst_n), .x(out), .out(x_out));

甲壳虫 · 发表于 2016-5-11 14:00:10

回复 2# huster 这个我知道，昨天也试着写了一下，但是总是出现错误，端口之间的到底该怎么链接啊。谢谢。

甲壳虫 · 发表于 2016-5-11 14:02:32

回复 3# haimo 试着用你的编译了一下有错误：Error (10663): Verilog HDL Port Connection error at sqrt.v(261): output or inout port "out" must be connected to a structural net expression。

haimo · 发表于 2016-5-12 09:06:52

cordic的输入连 input [15:0] out;
cordic的输出连谁？

[求助] 在Verilog中有关模块的例化问题。

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