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A 45-nm SOI-CMOS Dual-PLLProcessor Clock Systemfor Multi-Protocol I/O
First Time, Every Time –Practical Tips for PhaseLockedLoop Design
An On-Chip All-Digital MeasurementCircuit to Characterize Phase-LockedLoop Response in 45-nm SOI
Custom Integrated Circuits ConferenceSeptember 16, 2009
Dennis Fischette designs mixed-signal circuits at Advanced Micro Devices in Sunnyvale, CA. His technical interests include PLL and DLL design, clock-and-data recovery, circuit analysis software, and high-speed IO circuits. He is a member of the IEEE Distinguished Lecturer program as well as the CICC Technical Program Committee. He was a member of the ISSCC Technical Program Committee from 2001-2006.He graduated from Cornell University, Ithaca, NY, with Physics BSc in 1986. Before seeking fame and fortune in Silicon Valley, he pursued graduate studies in the History of Science at the University of California, Berkeley. Dennis is known to "toot his own horn" all over the SF Bay Area as a trombonist with several jazz ensembles. He recently toured China and Vietnam with the SFBayJazz big band. |
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发表于 2016-2-15 16:19:45
