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doomsten · 发表于 2015-10-11 19:10:39

我来介绍打开的原理 can_v5_0.vhd
`protect begin_protected
`protect version = 1
...........................
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
DAApHpRsqxwjwvK6twwZSkSDTRJ+XwytvkqnPPqhJSHz/mBj7ReIzCLMA2O2nRXamiAPqdFrhtfa
IX8DpRzNjLrbPbEKjg9npplejlcpzJjNdLd9Kums+Aj4OoJ6sWXldMzHm3t/l44i4LSie8AXTPOK
PHlpDNNDoYyLdQN0IcDTWtOjW5uY+7tajVRRnFrPQbhWRYUzqIxSZjCw6aAOczt9wB1TkG8eV5FT
qqOMhwKq0eoxABz6rOnO7jwnx4iZO/VbN02+9NPsNhl5sFnM6HKT8tSglyUPzfTWgReADlmrYIx9
aEvJAYZa4hx8DICa6k+SHBTRBZP7HfHw4/rh3A==

...................................

`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5728)
`protect data_block
Y+jlCwCJ2URLxdr0iREBbTEUpDPxwmY3NC64FQ6bkPOmmxuuOGjc7tE+6rAT4IumMCKfnukNBHCX
vH0tHSYanYQCLtYZZDaZZBJVUpFp3Qp13Q4TCPkPuz+qHInx/sUvhxWAQQr8hxfxQWAAW8YUl5Nv
dzkAQhF67VP3Fv2h4QlVwNON+p4KSqOii5iD1DvDYvDg1WOucayZaFqtZvBr0QhCzIlABlO/bdIV
eJ0SL+TePdcMdSHfjdpqVLHRcC3mH+1ZAAOdScSVmFtWayAK6vpqxWW4/g4njyFfwBy3GQI9oQdL
KP4INtrArTAQNzY//PP5SiaevOIa/32fjoW0e0OCGUofhCqDXp0AZMUExF1i8vqyiC47PPAwI8Jk

............................
1.从libisl_iostream.dll中找到RSA私钥,解开key_block下面的数据得到AES的密钥
2.用上面的密钥解开data_block下面的数据
编程可以使用openssl开源库，很简单。比较复杂的是找RSA那个私钥。
。。。。。
library ieee;
use ieee.std_logic_1164.all;

library can_v5_0;
use can_v5_0.all;

entity can_v5_0 is
generic (
      c_can_rx_dpth : integer := 64;
      c_can_tx_dpth : integer := 64;
      c_can_num_acf : integer := 4;
      c_c2s_mtbf_stages : integer := 2;
      c_s2c_mtbf_stages : integer := 2;
      c_s_axi_addr_width : integer := 8;
      c_s_axi_data_width : integer := 32;
      c_family : string := "virtex7"
);
port (
      can_clk : in std_logic := '0';
      can_phy_rx : in std_logic := '0';
      can_phy_tx : out std_logic;
      ip2bus_intrevent : out std_logic;
      s_axi_aclk : in std_logic := '0';
      s_axi_aresetn : in std_logic := '0';
      --s_axi_awaddr : in std_logic_vector(c_s_axi_addr_width - 1 downto 0) := (others => '0');
      s_axi_awaddr : in std_logic_vector(8 - 1 downto 0) := (others => '0');
      s_axi_awvalid : in std_logic := '0';
      s_axi_awready : out std_logic;
      --s_axi_wdata : in std_logic_vector(c_s_axi_data_width - 1 downto 0) := (others => '0');
      s_axi_wdata : in std_logic_vector(32 - 1 downto 0) := (others => '0');
      --s_axi_wstrb : in std_logic_vector((c_s_axi_data_width / 8 ) - 1 downto 0) := (others => '0');
      s_axi_wstrb : in std_logic_vector((32 / 8 ) - 1 downto 0) := (others => '0');
      s_axi_wvalid : in std_logic := '0';
      s_axi_wready : out std_logic;
      s_axi_bresp : out std_logic_vector(1 downto 0);
      s_axi_bvalid : out std_logic;
      s_axi_bready : in std_logic := '0';
      --s_axi_araddr : in std_logic_vector(c_s_axi_addr_width - 1 downto 0) := (others => '0');
      s_axi_araddr : in std_logic_vector(8 - 1 downto 0) := (others => '0');
      s_axi_arvalid : in std_logic := '0';
      s_axi_arready : out std_logic;
      --s_axi_rdata : out std_logic_vector(c_s_axi_data_width - 1 downto 0);
      s_axi_rdata : out std_logic_vector(32 - 1 downto 0);
      s_axi_rresp : out std_logic_vector(1 downto 0);
      s_axi_rvalid : out std_logic;
      s_axi_rready : in std_logic := '0'
);
end entity can_v5_0;

architecture xilinx of can_v5_0 is

attribute DowngradeIPIdentifiedWarnings: string;

attribute DowngradeIPIdentifiedWarnings of xilinx : architecture is "yes";

constant eval_tic_ps : integer := 10000;
begin
core_options : if true generate
      begin cantop_i : entity can_top
      generic map (
         c_can_rx_dpth => c_can_rx_dpth,
         c_can_tx_dpth => c_can_tx_dpth,
         c_can_num_acf => c_can_num_acf,