后端面试--每日一题（014）

ayowala · 发表于 2012-2-6 10:49:33

过来学习一下

xln610 · 发表于 2012-2-14 15:34:08

学习中。

真我个性 · 发表于 2015-8-10 20:23:07

摘录一段解释
Buffers versus inverters
As input goes into a buffer, the input of the first stage inverter, it only drives the output stage inverter with no wire. Therefore, buffer has a transition time recovery benefit to clock signals. If a slower transition gets feed into an inverter, the input slow transition will also affect the output transition time directly. This will cause more skew and jitters in the clock tree, especially, in the high level of clock tree, where long wire is predominant.

When the entire clock tree uses buffers only, at rise clock edge, all clock nets need to be charged up. VDD power net needs to provide the charge required to raise the entire clock nets. For inverters, input signal will switch in the opposite direction as the output. Therefore, when using inverters, the simultaneous switching power noise will be reduced.