DDR2控制器，时序约束时出错，有哪位大神帮帮忙？

JIANGXHUA · 发表于 2015-1-10 09:50:14

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

PhysDesignRules:2449 - The computed value for the VCO operating frequency of PLL_ADV instance
my_mig_inst/memc3_infrastructure_inst/u_pll_adv is calculated to be 119.999998 MHz. This falls below the operating
range of the PLL VCO frequency for this device of 400.000000 - 1080.000000 MHz. Please adjust either the input
frequency CLKINx_PERIOD, multiplication factor CLKFBOUT_MULT or the division factor DIVCLK_DIVIDE, in order to
achieve a VCO frequency within the rated operating range for this device.

时序约束时出现以上问题，该怎么办？