Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor

rockelin · 发表于 2014-11-26 16:32:53

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

Wafer-Level Chip-Scale Packaging_ Analog and Power Semiconductor Applications.pdf

A wafer-level chip-scale package (WLCSP) isa bare die package that offers notonly the smallest possible footprints in allIC package forms, but also superior electrical and thermal performance, mostlycredited to the direct solder interconnections that are low in electrical andthermal resistance and low in inductance

between chip and application PCB it isassembled on. For mobile electronics, where performance needs to be high andsize must be small, heat dissipation is limited to the conduction through PCBto the case of the mobile device; WLCSP is the best chip package option thatbalances the seemingly conflicting requirements.

Sharing the same root with the flip chippackage, WLCSP took a bold step forward by placing sufficient size solder bumpson a semiconductor chip and allowing it to be flip mounted directly on anapplication board. With solder joints taking up a significant portion ofchip/PCB CTE mismatching thermal/mechanical stresses, WLCSP has proved to bereliable in mobile-specific reliability tests, such as drop test, bending test,and temperature cycling tests, besides the basic devicespecific reliabilitytests. The robustness of this packaging form is also demonstrated with lastinglife of everyday use on billions of mobile consumer electronics devices.

With continuous evolvement in the bumpingtechnologies, such as polymer re-passivated bump on pad (BoP), copperredistribution layer (RDL), front side molded copper post on the RDL,aggressive silicon back grinding, advanced solder alloys, and design know-how,WLCSP has expanded the size range from early days under 2–3 mm to 8–10 mmsilicon chip size, while at the same time continuously reducing the per unitcost with scaling factors of high volume production in 200 and 300 mm wafersizes. The availability of package size range and favorable cost structuremakes WLCSP a good packaging candidate for a wide array of semiconductordevices, from analog/mixed signal and wireless connectivity chips tooptoelectronics, power electronics, and logic and memory chips. Innovations inwaferlevel 3D chip stacking further enable WLCSP a viable option for MEMS andsensor chip packaging.

The beauty of WLCSP is the start-to-finishwafer-based processing. It blurs the line between semiconductor wafer fabprocesses and the backend packaging operations. There is no singulated diepackaging operation typically seen in all other types of chip packagingoperations. WLCSP packaging operations, including bumping, inspections, andtests, are fully automated from cassette to cassette, book. They are theInstitute of Electrical and Electronic Engineers (IEEE) and its Conferences,Proceedings, and Journals, including IEEE Transactions on Components andPackaging Technology and IEEE Transactions on Electronics PackagingManufacturing. The authors also appreciate the following Conferences forallowing the reorganization and reproduction of previously published materials:IEEE Electronic Components and Technology Conference (ECTC), IEEE InternationalConference on Electronic Packaging Technology and High Density Packaging(ICEPT-HDP), and IEEE International Conference on Thermal, Mechanical andMult-Physics Simulation and Experiments in Microelectronics and Microsystems(EuroSimE).

Wafer-Level Chip-Scale Packaging_ Analog and Power Semiconductor Applications 2015.part1.rar (7 MB, 下载次数: 613 )

Wafer-Level Chip-Scale Packaging_ Analog and Power Semiconductor Applications 2015.part2.rar (7 MB, 下载次数: 548 )

Wafer-Level Chip-Scale Packaging_ Analog and Power Semiconductor Applications 2015.part3.rar (6.45 MB, 下载次数: 535 )