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本帖最后由 douwangdiaole 于 2014-11-25 23:24 编辑
本人一位硬件工程师,由于项目需要最近开始着手学FPGA,按照相关教程写了一个流水灯的程序,期间遇到了很多问题都慢慢的解决了,但是这次遇到了奇怪的问题不知道怎么处理。 本人将一个源码文件分成3个模块,之后设置一个top层文件挂载4个模块,编译之后报错一检查修改之后成功编译,但是综合的结果却很不可思议,硬件资源占用0%。
- Flow Status Successful - Sun Nov 23 20:15:04 2014
- Quartus II 32-bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
- Revision Name LED_Water
- Top-level Entity Name led_water
- Family Cyclone IV E
- Device EP4CE6E22C8
- Timing Models Final
- Total logic elements 0 / 6,272 ( 0 % )
- Total combinational functions 0 / 6,272 ( 0 % )
- Dedicated logic registers 0 / 6,272 ( 0 % )
- Total registers 0
- Total pins 11 / 92 ( 12 % )
- Total virtual pins 0
- Total memory bits 0 / 276,480 ( 0 % )
- Embedded Multiplier 9-bit elements 0 / 30 ( 0 % )
- Total PLLs 0 / 2 ( 0 % )
复制代码
首先top文件源码:
- module led_water(
- clock_50mhz,
- reset_n,
- key_s,
- led
- );
- input clock_50mhz;
- input reset_n;
- input key_s;
- output led;
-
- wire [7:0] led;
-
- led_display(
- .clock_50mhz (clock_50mhz),
- .led_clock (led_clock),
- .reset_n (reset_n),
-
- .key_s_flag (key_s_flag),
- .led (led)
- );
- key_scan(
- .clock_50mhz (clock_50mhz),
- .reset_n (reset_n),
- .key_s (key_s),
-
- .key_s_flag (key_s_flag)
- );
- sys_clock(
- .clock_50mhz (clock_50mhz),
- .reset_n (reset_n),
-
- .led_clock (led_clock)
- );
- endmodule
复制代码
模块1源码:
- module sys_clock(
- clock_50mhz,
- reset_n,
- led_clock
- );
- input clock_50mhz;
- input reset_n;
- output led_clock;
-
- wire clock_50mhz;
- reg [25:0] led_clock;
-
- always @ (posedge clock_50mhz or posedge !reset_n)
- begin
- if(!reset_n)
- led_clock <= 1'b0;
- else
- led_clock <= led_clock+1;
- end
- endmodule
-
复制代码
模块2源码:
- //定义函数
- module led_display(
- clock_50mhz,
- led_clock,
- reset_n,
- key_s_flag,
- led
- );
- //out or in port
- input clock_50mhz;
- input led_clock;
- input reset_n;
- input key_s_flag;
- output [7:0] led;
- //wire or register
- wire clock_50mhz;
- wire [7:0] led;
- //define register
- reg [7:0] led_data = 8'b1000_0000;
-
- always @ (posedge clock_50mhz or posedge !reset_n)
- begin
- if(!reset_n)
- led_data <= 1'b0;
- else if(key_s_flag)
- begin
- led_data[0] <= led_data[7];
- led_data[1] <= led_data[0];
- led_data[2] <= led_data[1];
- led_data[3] <= led_data[2];
- led_data[4] <= led_data[3];
- led_data[5] <= led_data[4];
- led_data[6] <= led_data[5];
- led_data[7] <= led_data[6];
- end
- end
- assign LED = led_data;
- endmodule
复制代码
模块3源码:
- module key_scan(
- clock_50mhz,
- reset_n,
- key_s,
- key_s_flag
- );
- input clock_50mhz;
- input key_s;
- input reset_n;
- output key_s_flag;
-
- reg key_s_flag;
-
- always @ (posedge clock_50mhz or posedge !reset_n or posedge !key_s)
- begin
- if(!reset_n)
- key_s_flag <= 0;
- else if(!key_s)
- key_s_flag <= 1;
- end
- endmodule
复制代码
项目源码在附件里面,希望多多提供改进意见,谢谢
02_KEY_LED.zip
(2.94 MB, 下载次数: 6 )
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