其实我主要最难懂的是那些寄存器的值该如何读取,比如说
if (Sn_MR(ALIGN) == ‘0’)
{
pack_size = Sn_RX_FIFOR; /* extract size of DATA packet from internal RX memory */
}
else
{
pack_size = Sn_RX_RSR; /* check the total received data size */
}
这其中的Sn_RX_FIFOR和Sn_RX_RSR怎么得到,verilog定义成变量又是不对的啊,那如何处理啊?