马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
Responsibilities: -Make verification plan for one module or whole chip. -Build up and maintain module-level and chip-level verificationenvironment -Verify ASIC digital design based on case list, and outputverification report. -Also responsible for lint checking and formal verification. Qualifications: -Proficiency in logic verification. -Experience with Verilog logic design language. -Experience with high-level verification languages such asSystem Verilog, System C, Vera or Specman e language. -Experience with UNIX/Linux simulation tools such as IUS orVCS. -Experience with C and C++ is a plus. -Experience with C_SHELL, TCL or PERL is a plus. -Experience with UVM, OVM or VMM is a plus. -Good knowledge of SOC design is a plus. -Good knowledge of software design is a plus. -Self-motivated and good team player. -MSEE or BSEE with 2+ years. |