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发表于 2014-5-15 22:19:40
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没做过,User guide上的一点信息供参考:The clock_opt command is multi voltage-aware. No special setup is required. The clock tree synthesis engine in IC Compiler recognizes the logic hierarchy associated with the voltage area and creates the clock tree bottom-up by clustering sink points from the samevoltage area. After the clock subtrees are built for each voltage area, clock tree synthesis joins the subtrees at the root of the clock net.
For bottom-up clock tree synthesis, IC Compiler performs endpoint clustering based on voltage areas. It builds a separate clock subtree for each voltage area, without crossovers between these subtrees.
You should insert level shifters and isolation cells as needed on clock nets that cross power domains before running clock tree synthesis. |
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