ERRORlace:1113 - Unroutable Placement! A BUFIO / PLL clock component pair have been found that are not placed at a
routable BUFIO / PLL site pair. The BUFIO component <SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_1> is placed at site
<BUFIO2_X3Y7>. The corresponding PLL component <u_pll1/pll_base_inst/PLL_ADV> is placed at site <LL_ADV_X0Y1>. The
BUFIO can use the fast path between the BUFIO and the PLL if the BUFIO is in TOPor BOTTOM edge and both the BUFIO &
PLL are placed in the same half of the device (TOP or BOTTOM). This placement is UNROUTABLE in PAR and therefore,
this error condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf
file to demote this message to a WARNING in order to generate an NCD file. This NCD file can then be used in FPGA
Editor to debug the problem. A list of all the COMP.PINS used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to demote this ERROR to a WARNING.
< PIN "u_pll1/pll_base_inst/PLL_ADV.CLKIN1" CLOCK_DEDICATED_ROUTE = FALSE; >
ERRORack:1654 - The timing-driven placement phase encountered an error.
log不是写了吗，直接ucf里添加括号里的约束
These
examples can be used directly in the .ucf file to demote this ERROR to a WARNING.
< PIN "u_pll1/pll_base_inst/PLL_ADV.CLKIN1" CLOCK_DEDICATED_ROUTE = FALSE; >
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发表于 2014-4-26 18:12:40
lace:1113 - Unroutable Placement! A BUFIO / PLL clock component pair have been found that are not placed at a
LL_ADV_X0Y1>. The
发表于 2014-4-30 16:08:46
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