请教关于always中敏感事件列表的问题

tianshilei1992

请教一下大家，如果我有三个信号：pa2, pa3, pa4，只有当他们同时都有下降沿的时候进入always语句，不知道这种的用Verilog该如何写？现在学到的只有or是“或”事件，而不是“与”事件，似乎在列表里面写and也会错误……

A1985

写行为还是RTL？

xushuai_hit53

你为什么不在always里面判断他们三个呢，如果是时序逻辑，敏感列表里放clk触发，而在always块里面进行对这个三个信号的沿检测而进行相应的判断，如果是组合逻辑没有必要在always块里执行。

goddade

同时下降。。怎么保证

wh1105

assumption: the pa2, pa3 and pa4 are same the clock domain

always @(posedge clk or negedge RESETN)
  if(~RESETN)
      signal_stb <= 1'b0;
  else if(pa2 & pa3 & pa3)
      signal_stb <= 1'b1;

wh1105

assumption: the pa2, pa3 and pa4 are the same clock domain

reg signal_stb;

always @(posedge clk or negedge RESETN)
  if(~RESETN)
     signal_stb <= 1'b0;
  else if(pa2 & pa3 & pa4)
     signal_stb <= 1'b1;
  else
     signal_stb <= 1'b0;

wh1105

assumption: the pa2, pa3 and pa4 are the same clock domain

reg signal_stb;

always @(posedge clk or negedge RESETN)
  if(~RESETN)
     signal_stb <= 1'b0;
  else if(pa2 & pa3 & pa4)
     signal_stb <= 1'b1;
  else
     signal_stb <= 1'b0;

wh1105

回复 1# tianshilei1992


   assumption: the pa2, pa3 and pa4 are the same clock domain

reg signal_stb;


always @(posedge clk or negedge RESETN)
  if(~RESETN)
     signal_stb <= 1'b0;
  else if(pa2 & pa3 & pa4)
     signal_stb <= 1'b1;
  else
     signal_stb <= 1'b0;

richardxingxing

应该是要先用一个高频时钟采样这三个信号，然后分别同步后作出一个上升沿脉冲，然后在高频采样时钟下着三个脉冲与一下

tianshilei1992

回复 2# A1985


   是RTL……