PSRR for an standard LDO is simple to derive and understand. For other topologies , one needs to derive the stuff, but intuitively following are true.
1.DC PSRR:Cascoding and increase channel length (take care of not pushing dominant pole inwards with too much output impedance)
2.AC PSRR would depend on the opamp unity gain bandwidth hence being able to push unity gain frequency as much as possible without being unstable is the key.More UGB requires more current to push out non dominant poles outward. Hence as always tradeoff between power dissipation and spec.
pole locations are as Follows: 1.Dominant pole is at the output (for substractor Topology) 2.Pole at the output of the error amplifier is Cancelled using ESR of Capacitor (Ceramic Capacitor) 3.Second non-dominant pole is due to PARASITIC Capacitance at the Pass device, can be pushed out of Unity Frequency to Ensure PhaseMargin> 45 deg. 4.Worst Case Stability condition arises during full load condition (at ILoad = Imax) 5.Consumes More Quiscent Current Because the Subtractor Mirrors some More current.
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2013-11-22 14:59:21
