回复 18# whitetiger
This position of “R&D Engineer, II” is an ASIC/Digital Design & Verification Engineer whose mandate is to participate in the design of semiconductor integrated circuits in compliance with the project’s specifications and Synopsys’ design methodologies. The successful candidate will work on a variety of design and verification tasks, incorporating such tasks as, and not limited to, RTL coding, behavioural coding, testbench and testcase generation, RTL simulation, synthesis, STA, gate-level simulation, formal verification, documentation, and prototype evaluation. The duties performed by the R&D Engineer I, will include, though not be limited to: ·
Understand design specifications. ·
Write synthesizable RTL code for circuit portions of integrated circuits. ·
Write behavioural models. ·
Generate testbenches and testcases. ·
Perform complex RTL simulations of circuits, interpret the results and optimize the code until the predetermined functionality is satisfied. ·
Generate timing constraints for synthesizable designs. ·
May perform logic synthesis and/or static timing analysis. ·
Perform gate-level simulations of circuits, interpret the results and optimize the design until the predetermined functionality and timing is satisfied. ·
May perform mixed-mode simulations. ·
Documentation of functionality, code, verification environments/plans, and design procedures. ·
May participate in prototype evaluation using bench top laboratory instruments or automated test equipment. ·
Communicate with other Synopsys employees regarding customer technical support. ·
May communicate directly with customers regarding technical support. ·
Other related duties as assigned by the manager. The position of R&D Engineer II requires a degree in Engineering or Applied Science (or equivalent) and 2+ years working experience in a related field as well as familiarity with both verilog circuit design and design verification and with generation of timing constraints for ASIC designs. |