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我现在找到了verilog程序,我需要综合看电路图,求大神帮忙
module ALU_Demo_1(
A,B,Ci,//
D,//
Fc,//
cf,zf,sf,of//
);
input [15:0] A,B;
input Ci;
output[15:0] D;
input [ 2:0] Fc;
output cf,zf,sf,of;
reg [15:0] G,P;
wire [16:0] C;
// Fc G P Cp Descript
// 000 A & B A | B 0 A + B
// 001A & (~ B) A | (~ B) 1A - B
// 010 A & B A | B Ci A + B + Ci
// 011A & (~ B) A | (~ B) (~ Ci) A - B - Ci
// 100 A & B 0 X A & B
// 1010 A | B X A | B
// 110 A & B A | B X A ^ B
// 111A & B A | B X A ^ B
//----generat the G
always @(Fc or A or B)
casex(Fc)
3'b000: G = A & B;
3'b001: G = A & (~ B);
3'b010: G = A & B;
3'b011: G = A & (~ B);
3'b100: G = A & B;
3'b101: G = {16{1'b0}};
3'b110: G = A & B;
3'b111: G = A & B;
default: G = A & B;
endcase
//----generat the P
always @(Fc or A or B)
casex(Fc)
3'b000: P = A | B;
3'b001: P = A | (~ B);
3'b010: P = A | B;
3'b011: P = A | (~ B);
3'b100: P = {16{1'b0}};
3'b101: P = A | B;
3'b110: P = A | B;
3'b111: P = A | B;
default: P = A | B;
endcase
//----generat the C in leading carry link
wire Cp;
wire [ 3:0] Gl,Pl;
wire [ 4:1] Cx;
wire [16:1] Ct;
assign Cp = ((Ci & Fc[1]) ^ Fc[0]);
Carry_Leading_4 CL0 (G[ 3: 0],P[ 3: 0],Cp ,Ct[ 4: 1],Gl[0],Pl[0]);
Carry_Leading_4 CL1(G[ 7: 4],P[ 7: 4],Cx[1],Ct[ 8: 5],Gl[1],Pl[1]);
Carry_Leading_4 CL2 (G[11: 8],P[11: 8],Cx[2],Ct[12: 9],Gl[2],Pl[2]);
Carry_Leading_4 CL3 (G[15:12],P[15:12],Cx[3],Ct[16:13],Gl[3],Pl[3]);
Carry_Leading_4 CLX (Gl[ 3:0],Pl[ 3:0],Cp,Cx[ 4:1],,);
//assign C = {Ct,Cp};
assign C = {Cx[4],Ct[15:13],Cx[3],Ct[11:9],Cx[2],Ct[7:5],Cx[1],Ct[3:1],Cp};
//----generate the result
assign D = G ^ P ^ ((~ Fc[2]) ? C[15:0] : {16{1'b0}});
assign cf = (C[16] ^ Fc[0]) & (~ Fc[2]);
assign zf = ! D;
assign sf = G[15] ^ P[15] ^ ((~ Fc[2]) & C[16]);
assign of = (C[15] ^ C[16]) & (~ Fc[2]);
endmodule
module Carry_Leading_4 (G,P,Ci,C,Gl,Pl);
input [ 3:0] G,P;
output [ 4:1] C;
input Ci;
output Gl,Pl;
wire [ 3:0] G,P;
wire [ 4:1] C;
wire Ci;
wire Gl,Pl;
assign C[1] = G[0] | P[0] & Ci;
assign C[2] = G[1] | P[1] & G[0] | P[1] & P[0] & Ci;
assign C[3] = G[2] | P[2] & G[1] | P[2] & P[1] & G[0] | P[2] & P[1] & P[0] & Ci;
assign C[4] = Gl | Pl & Ci;
assign Gl = G[3] | P[3] & G[2] | P[3] & P[2] & G[1] | P[3] & P[2] & P[1] & G[0];
assign Pl = P[3] & P[2] & P[1] & P[0];
endmodule |