求教如何减小电源和地的抖动

zygckj

请问一下，我设计的反相器与与非门组成的阵列，输入的是2.4Ghz信号，后仿发现电源和地的抖动很大，无法正常工作，是在电源和地的两根棒线间接个大电容吗？求大神指教

hezudao

没电容高频charge 谁提供？

semico_ljj

是什么电路？ 环形震荡还是buffer 整形？

朱立平

Use very wide power & ground metal line (top metal is better, or parallel top metal with other layer metal) direct feed power current from power & ground PAD, you can use large decopling cap. near your osc circuit. If floor plan is possible, place your circuit near power & ground PAD. Your power & ground pin outside IC should decoupling with 0.1uF cap. parallel with 1uF+ cap. 0.1uF cap on PCB shoule be very cloce to IC pin. Or you can use double bound of VDD & GND. Do you simulate the bounding wire effect?

朱立平

could you post the simulation voltage & current waveform of the power & ground ?

zygckj

回复 5# 朱立平


   谢了，的确是电源线很窄，压降有点大，我用了宽的电源线，用ADS看了下，电源端的频谱，噪声还是很大，我是用反相器驱动后面的mos管

v2是电源端，g2是地端，都是加了棒线后的图形

朱立平

Do you use inverter output as the power to feed the other circuit block?
If the answar is yes. Please enlarge your inverter PMOS size (enlarge W, minimum size L), NMOS is no matter (it is off in your case), then put a capacitor (top plate connect to inverter output, buttom connect to GND, keep metal wider) after the inverter, the capacitor (MIM, PIP or MOS cap. MIM is beter, try 10pF level) should be placed near the post circuit. Maybe you can series a small R (10~100 ohm) after inverter, before capacitor.

Check the waveform of the inverter input, if it is also noisely. Put a capacitor with top plate connect to the inv`s input and enlarge it`s driver. The driver`s GND (wider is better) line should direct connect to clean GND PAD or GND PAD. VDD should direct connect to  VDD PAD with another line (wider is better).
Analog block should use higher voltage, try to suggest your boss use larger VDD.

From your waveform your inverter`s input is also noisely. It is coupled from inv`s output by parasitic cap. & power rail (GND).

zygckj

回复 7# 朱立平


   我是输入横幅的正弦波信号，输出方波信号控制mos管，是做功放电路，总共分成19个控制端，你的意思是在每个控制端反相器后面都并联一个电容到地吗？那会不会太多啦，每个反相器接的是的是160u宽的管子的栅极，反相器nmos尺寸已经有20多u了，很大了

朱立平

You can use smaller NMOS in the inv. since it is no use in your case. Maybe w=2u.

Since your PMOS`s Vgs always transition,then PMOS`s rds is not constant, if you make PMOS`s behavior like a constant R maybe the effect will decrease.

Try to put capacitor before the inv`s input maybe 10 times larger of (PMOS`s Cgtot) between inv`s PMOS`s gate & source (Make PMOS`s Vgs as constant, then rds is constant). Every inv`s  PMOS use how well (NO body effect). Let every PMOS`s Vsb = 0, seperate every inv PMOS`s NWELL. use very weak driver (small W, large L) to drive the inv, maybe you can series a large resistor (or NMOS with large L & small W) to lower the transition effect from driver.

朱立平

Maybe you can use a small boost circuit to increase the PMOS`s NWELL voltage when it is turn on, then you can make your PMOS`s size smaller.