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FormalPro™ is the Mentor Graphics solution for gate-level regression testing of ASICs and ICs of 100,000 gates or more. FormalPro uses static formal verification techniques to prove that a design is functionally identical to its golden reference.- Dramatically Reduces ASIC/FPGA Verification Time
- Compares two designs
- RTL to gate for synthesis and ECOs
- Gate to gate for layout spins
- RTL to RTL for language conversion - Highest capacity tool
- Verifies multi-million gate
- ASIC's as one - Fastest route to correct design
- Exact location of errors
- Tests fixes within the verification session - Advanced FPGA Support
- Xilinx, Altera, Actel
- FVI and VIF automated setup files
- Huge productivity boost
在终端直接运行exe安装，破解把文件包里，含有破解说明！ |
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发表于 2012-9-24 21:20:07
