ESD (High-Speed_High-Frequency IO Interfaces)(RF) by Ker 2007

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ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-
Frequency I/O Interfaces in Integrated Circuits

Ming-Dou Ker* and Yuan-Wen Hsiao

Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, 1001 TA-Hsueh Road,
Hsinchu, Taiwan

Received: December 13, 2006; Accepted: April 4, 2007; Revised: April 4, 2007


Abstract:

Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics,
especially for integrated circuits (ICs). ESD protection design for giga-Hz high-speed input/output (I/O) circuits has been
one of the key challenges to implement high-speed interface circuits in CMOS technology. Conventional on-chip ESD
protection circuits at the I/O pads often cause unacceptable performance degradation to high-speed I/O circuits. Therefore,
ESD protection circuits must be designed with minimum negative impact to the high-speed interface circuits and to
sustain high enough ESD robustness. In this paper, ESD protection design considerations for high-speed I/O circuits are
addressed, and the patents related to on-chip ESD protection designs for high-speed I/O circuits are presented and
discussed

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Keywords:

Electrostatic discharge (ESD), input/output (I/O) interface, low capacitance (low-C), power-rail ESD clamp circuit, LC resonator,
LC-tank, impedance cancellation, impedance isolation, impedance matching, distributed ESD protection scheme, substrate-triggering
technique, silicon-controlled rectifier (SCR), waffle structure.

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CONCLUSION

A comprehensive overview on the recent patents in the field of
ESD protection design for high-speed or high-frequency I/O
circuits has been presented. The requirements on ESD protection
design for high-speed/high-frequency I/O circuits include low
parasitic capacitance, low loss, and high ESD robustness. To
optimize both high-speed circuit performance and high enough
ESD robustness simultaneously, the undesired parasitic effects from
ESD protection devices must be minimized or cancelled. Furthermore,
the ESD protection circuits and high-speed I/O circuits
should be co-designed to achieve both good circuit performance
and high ESD robustness. As the operating frequencies of ICs are
further increased, on-chip ESD protection design for highspeed/
high-frequency I/O applications will continuously be an
important design task

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This paper presents an overview on the ESD protection designs for high-speed I/O circuits, which have been granted with U.S. patents. The design considerations on ESD protection circuits for high-speed I/O applications are discussed in Section 2. The granted U.S. patents about ESD protection designs by circuit solutions, layout solutions, and process solutions are presented and discussed in Sections 3, 4, and 5, respectively. Finally, the current and future developments, and conclusion are provided in Sections 6 and 7, respectively.

sawfish

Thanks!

mingho

thanks

mingho

thanks for sharing

alex_bai

mryu

xiexie lao da