ESD 柯明道－－High-Voltage Tolerance I/O ESD防护（繁体中文）

semico_ljj

ESD 柯明道－－High-Voltage Tolerance I/O ESD防护（繁体中文）

摘要
高低壓共容輸出入界面(High-Voltage Tolerance I/O)電路的靜電放電(ESD)防
護能力遠低於一般傳統的輸出入電路(Regular I/O Circuits)。造成高低壓共容輸出
入界面電路的低靜電放電防護能力的主要原因，就是串疊結構的N 型金氧半電
晶體中的第一個閘極(Gate)端，將被耦合到一高電位。如此高耦合電位將會觸發
較高的電晶體通道電流(Channel Current)。高的通道電流是造成串疊結構N 型金
氧半電晶體低靜電放電防護能力的主要原因之一。除了發現閘極端的電位增加是
造成低靜電放電防護能力外。另有一項因素，增加汲極(Drain)端的非金屬矽化區
(Non-Silicide)的寬度，將可有效降低閘極端高電壓對靜電放電不利的影響。掌握
以上兩項因素將可有效提升高低壓共容輸出入界面電路的靜電放電防護能力。

semico_ljj

Reference:
[1] Warren R. Anderson and David B. Krakauer, “ESD protection for mixed-voltage I/O using NMOS transistors
stacked in a cascode configuration,” in Proc. ESD/EOS Symp., 1998, pp. 54-62.
[2] James W. Miler, Michael G. Khazhinsky, and James C. Weldon, “Engineering the cascoded NMOS output
buffer for maximum Vt1,” in Proc. ESD/EOS Symp., 2000, pp. 308-317.
[3] M.-D. Ker and C.-H. Chang, “Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in
high/low-voltage-tolerant I/O interface,” IEEE Electron Device Lett. vol. 23, pp. 363-365, Jun. 2002.
[4] C. Hashimoto, K. Okuyama, K. Kubota, and H. Ishizuka, “Degradation of I/O devices due to ESD-induced
dislocations,” in IEDM Tech. Dig., 1994, pp.459-462.

semico_ljj

Stacked-NMOS Triggered Silicon-Controlled
Rectifier for ESD Protection in
High/Low-Voltage-Tolerant I/O Interface

Ming-Dou Ker, Senior Member, IEEE, and Chien-Hui Chuang

Abstract—A stacked-NMOS triggered silicon-controlled rectifier
(SNTSCR) is proposed as the electrostatic discharge (ESD)
clamp device to protect the mixed-voltage I/O buffers of CMOS
ICs. This SNTSCR device is fully compatible to general CMOS
processes without using the thick gate oxide to overcome the gateoxide
reliability issue. ESD robustness of the proposed SNTSCR
device with different layout parameters has been investigated in a
0.35- m CMOS process. The HBM ESD level of the mixed-voltage
I/O buffer with the stacked-NMOS channel width of 120 m can
be obviously improved from the original 2 kV to be greater
than 8 kV by this SNTSCR device with a device dimension of only
60 m 0 35 m.

Index Terms—Electrostatic discharge (ESD), ESD protection,
mixed-voltage I/O buffer, silicon-controlled rectifier (SCR).

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IV. CONCLUSION
The – characteristics of the new SNTSCR device for
on-chip ESD protection under different gate biases and layout
parameters have been investigated in details in CMOS process.
This SNTSCR device can sustain a much higher ESD level
within a much smaller layout area, which is very attractive to
modern high-integration SoC. Without using the thick gate
oxide, this SNTSCR device is fully process-compatible to
general subquarter-micron CMOS processes for effectively
protecting the mixed-voltage interface circuits against ESD
damage.

zhanweisu27

什么时候发表的，可能已经有了

flyfeng

谢谢了

alex_bai

enewbox

thanks for sharing!!!

charlie11

wc200305

thanks !!!