某cell部分module path sdf反标不上

my2817 · 发表于 2012-7-31 16:05:39

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本帖最后由 my2817 于 2012-7-31 16:21 编辑

--------------小弟在此开贴求助------------------------------------还请各位赐教-----------------------
--------------内容看着挺多，但关键问题没多少--------

NC-verilog在某Design的后仿中，发现某一cell的部分 module path SDF反标不成功，，现在将该cell及其在design中的SDF信息摘录出来分析，详情如下：

该cell的function 定义如下：

module HDR_MUX3_1( I0, I1, S0, S1, I2, Z);
input I0, I1, S0, S1, I2;
output Z;
`ifdef FUNCTIONAL // functional //
`else
HDR_MUX3_1$func HDH_MUX3_1_inst(.I0(I0),.I1(I1),.S0(S0),.S1(S1),.I2(I2),.Z(Z));
`endif
`ifdef FUNCTIONAL // functional //
HDR_MUX3_1$func HDH_MUX3_1_inst(.I0(I0),.I1(I1),.S0(S0),.S1(S1),.I2(I2),.Z(Z));
`endif
`ifdef FUNCTIONAL // functional //
`else
// specify block begins
specify
if(I1===1'b0 && I2===1'b0)
// arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b0 && I2===1'b1)
// arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b0)
// arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b1)
// arc I0 --> Z
(I0 => Z) = (1.0,1.0);
ifnone
// arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b0)
// arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b1)
// arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b0)
// arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b1)
// arc I1 --> Z
(I1 => Z) = (1.0,1.0);
ifnone
// arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && S0===1'b0)
// arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && S0===1'b1)
// arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && S0===1'b0)
// arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && S0===1'b1)
// arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && S0===1'b0)
// arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && S0===1'b1)
// arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && S0===1'b0)
// arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && S0===1'b1)
// arc I2 --> Z
(I2 => Z) = (1.0,1.0);
ifnone
// arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I2===1'b0)
// arc posedge S0 --> (Z:S0)
(posedge S0 => (Z:S0)) = (1.0,1.0);
if(I2===1'b0)
// arc negedge S0 --> (Z:S0)
(negedge S0 => (Z:S0)) = (1.0,1.0);
if(I2===1'b1)
// arc posedge S0 --> (Z:S0)
(posedge S0 => (Z:S0)) = (1.0,1.0);
if(I2===1'b1)
// arc negedge S0 --> (Z:S0)
(negedge S0 => (Z:S0)) = (1.0,1.0);
// arc posedge S0 --> (Z:S0)
(posedge S0 => (Z:S0)) = (1.0,1.0);
// arc negedge S0 --> (Z:S0)
(negedge S0 => (Z:S0)) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && S0===1'b1)
// arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && S0===1'b0)
// arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && S0===1'b0)
// arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && S0===1'b1)
// arc S1 --> Z
(S1 => Z) = (1.0,1.0);
// arc posedge S1 --> (Z:S1)
(posedge S1 => (Z:S1)) = (1.0,1.0);
// arc negedge S1 --> (Z:S1)
(negedge S1 => (Z:S1)) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && S0===1'b0)
// arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && S0===1'b1)
// arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && S0===1'b0)
// arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && S0===1'b1)
// arc S1 --> Z
(S1 => Z) = (1.0,1.0);
endspecify
`endif
endmodule

复制代码

当然还有其HDR_MUX3_1$func就不在些贴出来了，然后是design中关于该cell的sdf描述：

(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "tchip_hlmc55lp_top")
(DATE "Fri Feb 24 11:31:01 2012")
(VENDOR "Cadence Design Systems, Inc.")
(PROGRAM "Encounter")
(VERSION "v10.11-s096_1 ((64bit) 03/23/2011 02:21 (Linux 2.6))")
(DIVIDER /)
(VOLTAGE 1.200000::1.200000)
(PROCESS "1.000000::1.000000")
(TEMPERATURE 25.000000::25.000000)
(TIMESCALE 1.0 ns)
(CELL
(CELLTYPE "HDR_MUX3_1")
(INSTANCE )
(DELAY
(ABSOLUTE
(IOPATH (negedge S1) Z (0.208::0.208) (0.226::0.226))
(IOPATH (posedge S1) Z (0.232::0.232) (0.195::0.195))
(COND I0===1'b1&&I1===1'b1&&S0===1'b1 (IOPATH S1 Z (0.208::0.208) (0.195::0.195)))
(COND I0===1'b1&&I1===1'b1&&S0===1'b0 (IOPATH S1 Z (0.208::0.208) (0.195::0.195)))
(COND I0===1'b1&&I1===1'b0&&S0===1'b0 (IOPATH S1 Z (0.208::0.208) (0.195::0.195)))
(COND I0===1'b0&&I1===1'b1&&S0===1'b1 (IOPATH S1 Z (0.208::0.208) (0.195::0.195)))
(COND I0===1'b1&&I1===1'b0&&S0===1'b1 (IOPATH S1 Z (0.232::0.232) (0.226::0.226)))
(COND I0===1'b0&&I1===1'b1&&S0===1'b0 (IOPATH S1 Z (0.232::0.232) (0.226::0.226)))
(COND I0===1'b0&&I1===1'b0&&S0===1'b1 (IOPATH S1 Z (0.232::0.232) (0.226::0.226)))
(COND I0===1'b0&&I1===1'b0&&S0===1'b0 (IOPATH S1 Z (0.232::0.232) (0.226::0.226)))
(IOPATH (posedge S0) Z (0.219::0.219) (0.257::0.257))
(IOPATH (negedge S0) Z (0.254::0.254) (0.237::0.237))
(COND I2===1'b1 (IOPATH (posedge S0) Z (0.210::0.210) (0.257::0.257)))
(COND I2===1'b1 (IOPATH (negedge S0) Z (0.245::0.245) (0.237::0.237)))
(COND I2===1'b0 (IOPATH (posedge S0) Z (0.219::0.219) (0.253::0.253)))
(COND I2===1'b0 (IOPATH (negedge S0) Z (0.254::0.254) (0.233::0.233)))
(IOPATH I2 Z (0.215::0.215) (0.213::0.213))
(COND I0===1'b1&&I1===1'b1&&S0===1'b1 (IOPATH I2 Z (0.197::0.197) (0.208::0.208)))
(COND I0===1'b1&&I1===1'b1&&S0===1'b0 (IOPATH I2 Z (0.197::0.197) (0.208::0.208)))
(COND I0===1'b1&&I1===1'b0&&S0===1'b1 (IOPATH I2 Z (0.215::0.215) (0.213::0.213)))
(COND I0===1'b1&&I1===1'b0&&S0===1'b0 (IOPATH I2 Z (0.197::0.197) (0.208::0.208)))
(COND I0===1'b0&&I1===1'b1&&S0===1'b1 (IOPATH I2 Z (0.197::0.197) (0.208::0.208)))
(COND I0===1'b0&&I1===1'b1&&S0===1'b0 (IOPATH I2 Z (0.215::0.215) (0.213::0.213)))
(COND I0===1'b0&&I1===1'b0&&S0===1'b1 (IOPATH I2 Z (0.215::0.215) (0.213::0.213)))
(COND I0===1'b0&&I1===1'b0&&S0===1'b0 (IOPATH I2 Z (0.215::0.215) (0.213::0.213)))
(IOPATH I1 Z (0.279::0.279) (0.301::0.301))
(COND I0===1'b1&&I2===1'b1 (IOPATH I1 Z (0.271::0.271) (0.301::0.301)))
(COND I0===1'b1&&I2===1'b0 (IOPATH I1 Z (0.279::0.279) (0.297::0.297)))
(COND I0===1'b0&&I2===1'b1 (IOPATH I1 Z (0.262::0.262) (0.267::0.267)))
(COND I0===1'b0&&I2===1'b0 (IOPATH I1 Z (0.270::0.270) (0.263::0.263)))
(IOPATH I0 Z (0.309::0.309) (0.306::0.306))
(COND I1===1'b1&&I2===1'b1 (IOPATH I0 Z (0.301::0.301) (0.306::0.306)))
(COND I1===1'b1&&I2===1'b0 (IOPATH I0 Z (0.309::0.309) (0.301::0.301)))
(COND I1===1'b0&&I2===1'b1 (IOPATH I0 Z (0.299::0.299) (0.289::0.289)))
(COND I1===1'b0&&I2===1'b0 (IOPATH I0 Z (0.308::0.308) (0.285::0.285)))
)
)
)
)

复制代码

对该cell建单独的仿真模型如下：

module HDR_MUX3_1_test_Z;
HDR_MUX3_1 instance0(.I0(I0), .I1(I1), .I2(I2), .S0(S0), .S1(S1), .Z(Z));
HDR_MUX3_1_stim_Z instance1(.I0(I0), .I1(I1), .I2(I2), .S0(S0), .S1(S1), .Z(Z));
initial begin
$sdf_annotate("./mux3_1.sdf",instance0,,"lsdf.og.log","MAXIMUM");
end
endmodule
module HDR_MUX3_1_stim_Z(I0,I1,I2,S0,S1,Z);
output I0,I1,I2,S0,S1;
reg I0,I1,I2,S0,S1;
input Z;
reg [0:5] vectors[0:431];
reg [0:5] ivector;
integer i_Y;
initial begin
vectors[0] = 6'b000000;
vectors[1] = 6'b100001;
vectors[2] = 6'b001000;
vectors[3] = 6'b101001;
vectors[4] = 6'b010000;
vectors[5] = 6'b110001;
vectors[6] = 6'b011000;
for(i_Y = 0; i_Y <432; i_Y = i_Y + 1)
begin
ivector = vectors[i_Y];
{I0,I1,I2,S0,S1} = ivector[0:4];
#20 ;
if( ivector[5] !== Z && ivector[5] !==1'bx)
$display("verify ERROR : HDR_MUX3_1:Z output mismatch at vector no. %d, %b != %b ",
i_Y,ivector[5], Z);
end
end
endmodule

复制代码

NC在执行 ncelab后，出现如下warning

ncelab: *W,SDFNEP: Unable to annotate to non-existent path (IOPATH (negedge S1) Z) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 19>.ncelab: *W,SDFNEP: Unable to annotate to non-existent path (COND (((I0===1)&&(I1===1))&&(S0===1)) (IOPATH S1 Z)) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 21>.ncelab: *W,SDFNEP: Unable to annotate to non-existent path (COND (((I0===1)&&(I1===1))&&(S0===0)) (IOPATH S1 Z)) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 22>.ncelab: *W,SDFNEP: Unable to annotate to non-existent path (COND (((I0===1)&&(I1===0))&&(S0===0)) (IOPATH S1 Z)) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 23>.ncelab: *W,SDFNEP: Unable to annotate to non-existent path (COND (((I0===0)&&(I1===1))&&(S0===1)) (IOPATH S1 Z)) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 24>.ncelab: *W,SDFNEP: Unable to annotate to non-existent path (COND (((I0===1)&&(I1===0))&&(S0===1)) (IOPATH S1 Z)) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 25>.ncelab: *W,SDFNEP: Unable to annotate to non-existent path (COND (((I0===0)&&(I1===1))&&(S0===0)) (IOPATH S1 Z)) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 26>.ncelab: *W,SDFNEP: Unable to annotate to non-existent path (COND (((I0===0)&&(I1===0))&&(S0===1)) (IOPATH S1 Z)) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 27>.ncelab: *W,SDFNEP: Unable to annotate to non-existent path (COND (((I0===0)&&(I1===0))&&(S0===0)) (IOPATH S1 Z)) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 28>.ncelab: *W,SDFNEP: Unable to annotate to non-existent path (IOPATH (negedge S0) Z) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 30>.ncelab: *W,SDFNEP: Unable to annotate to non-existent path (COND (I2===1) (IOPATH (negedge S0) Z)) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 32>.ncelab: *W,SDFNEP: Unable to annotate to non-existent path (COND (I2===0) (IOPATH (negedge S0) Z)) of instance HDR_MUX3_1_test_Z.instance0 of module HDR_MUX3_1 <./net/mux3_1.sdf, line 34>.

复制代码

目前还没分析出是什么原因造成的，还请赐教，

my2817 · 发表于 2012-7-31 16:25:56

--------------小弟在此开贴求助------------------------------------还请各位赐教---------------------- ...
my2817 发表于 2012-7-31 16:05

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我尝试用 modelsim仿真，其log如下

# ** Warning: (vsim-3010) [TSCALE] - Module 'HDR_MUX3_1' has a `timescale directive in effect, but previous modules do not.
# Region: /HDR_MUX3_1_test_Z/instance0
# Loading work.HDR_MUX3_1$func
# Loading work.HDR_MUX3_1_stim_Z
# ** Warning: (vsim-3009) [TSCALE] - Module 'HDR_MUX3_1_stim_Z' does not have a `timescale directive in effect, but previous modules do.
# Region: /HDR_MUX3_1_test_Z/instance1
# ** Warning: (vsim-PLI-3028) /home/users/heyun/Desktop/els/modelsim/MUX3_1_SIM.v(8): $sdf_annotate : 4th argument (log file) is not supported.
# Region: /HDR_MUX3_1_test_Z
# Loading instances from ./mux3_1.sdf
# Loading work.TT_HDR_MUX3_1_UDP_0
# Loading timing data from ./mux3_1.sdf
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# Time: 0 ps Iteration: 0 Region: /HDR_MUX3_1_test_Z File: /home/users/heyun/Desktop/els/modelsim/MUX3_1_SIM.v

复制代码

这是不是说明在modelsim中是反标成功了？

71875456 · 发表于 2014-3-18 15:21:40

大哥，一楼的问题解决了吗？我也遇到了。

黑色快乐 · 发表于 2018-4-17 14:51:07

还有回复么

[求助] 某cell部分module path sdf反标不上

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