Verilog后防时关于specify和延迟的权威资料

softhit

VlogTimingChecks.pdf (353.8 KB, 下载次数: 488 )

2012-7-10 16:25 上传

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Verilog Timing

$hold $nochange  $period $recovery $recrem $removal $setup $setuphold $skew $width
VlogDelays.pdf (308 KB, 下载次数: 412 )

2012-7-10 16:26 上传

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Verilog Delay

Interconnect Delays


❑ Default Interconnect Delays
❑ Interconnect Delays and -intermod_path
❑ Pulse Handling
❑ SDF Annotation of Interconnect Delays
❑ PLI Annotation of Interconnect Delays


    Module Path Delays


❑ Specify Blocks
❑ Describing Module Paths
❑ Establishing Full or Parallel Connection Paths
❑ Assigning Delays to Module Paths
❑ Selecting a Delay When Multiple Delays Are Specified for a Path
❑ Specify Properties for Module Path Delays
❑ Mixing Module Path Delays and Distributed Delays
❑ Strength Changes on Path Inputs
❑ Driving Wired Logic Outputs
❑ Simulating Path Outputs That Drive Other Path Outputs
❑ Enhancing Path Delay Accuracy
❑ SDF Annotation of Module Path Delays

nico0811

GOOD,3X

sdc19821006

咱也来学习下！

mzsm1

直接说cadence的资料就行了

freedos

这个是哪个版本的？

wangjunweiair

咱也来学习下！

comeon_lsl

学习下1！ 前一段，搞后仿，感觉好多东西待学！

blueeagle

好东西，谢谢楼主！

dcircuit

来学习下！

atonal

下载了学习，谢谢楼主。