为何要使用nanosim

morrisgu

SOC设计后面的阶段，导出sdf进行PT仿真不可以signoff吗？
和nanosim有何区别？

lmcon223

Take nanosim as a fast spice ( but may not as accurate as spice ). Though we say "fast", it's still slow compared to gate level simulation. Use or not according to project need.

morrisgu

回复 3# lmcon223

同感。
另外就是我感觉，PT + 后端sdf 是gate level级，而 nanosim 是 Post layout transistor-level 级，而且可以加vector，查看power和SI 方面的信息。但就是想知道nanosim是不是一定要跑，如果项目时间紧的话，是不是就跳过去了。

lmcon223

回复 4# morrisgu


    For mixed-signal design, if the interface or interference behavior of analog/custom block can be signoff-ed alone, that dramatically reduces the need of full chip transistor level simulation of function.
    But for the dynamic power analysis of full chip, especially for real functional patterns, nanosim or similar tools count.

歪枣树

回复 5# lmcon223


   nanosim ultrasim 各有什么优缺点？

conniezhou

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