请教高手DDR2内存条ModelSim仿真问题！！！

sgx7448350

最近在用ModelSim仿真 DDR2内存条部分，内存条模型是Micron公司的1G内存条，FPGA是Stratix IIGX系列的，现在遇到一个问题，仿真中向DDR2中写数据DQ DQS信号有输出正常，当时读数的时候一直是"zzzz"高阻状态。

PS：Quartus II 生成的DDR2部分的测试逻辑在我的电路板上已经用过了，用Signal Tab II测试写入和读出的数据相同。

现在modelsim中出现一些警告：
# ** Warning: (vsim-3017) ../../ddr2_ctrl_auk_ddr_clk_gen.v(66): [TFMPC] - Too few port connections. Expected 12, found 8.
#         Region: /ddr2_top_tb/dut/ddr2_ctrl_ddr_sdram/nll0lO/ddr_clk_gen/ddr_clk_out_p
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_clk_gen.v(66): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_clk_gen.v(66): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_clk_gen.v(66): [TFMPC] - Missing connection for port 'hrbypass'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_clk_gen.v(66): [TFMPC] - Missing connection for port 'oe_out'.
# ** Warning: (vsim-3017) ../../ddr2_ctrl_auk_ddr_clk_gen.v(87): [TFMPC] - Too few port connections. Expected 12, found 8.
#         Region: /ddr2_top_tb/dut/ddr2_ctrl_ddr_sdram/nll0lO/ddr_clk_gen/ddr_clk_out_n
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_clk_gen.v(87): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_clk_gen.v(87): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_clk_gen.v(87): [TFMPC] - Missing connection for port 'hrbypass'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_clk_gen.v(87): [TFMPC] - Missing connection for port 'oe_out'.
# ** Warning: (vsim-3017) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Too few port connections. Expected 12, found 8.
#         Region: /ddr2_top_tb/dut/ddr2_ctrl_ddr_sdram/nll0lO/\g_datapath:0

                               
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_ddr_io /dm_pin
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'hrbypass'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'oe_out'.
# ** Warning: (vsim-3017) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Too few port connections. Expected 12, found 8.
#         Region: /ddr2_top_tb/dut/ddr2_ctrl_ddr_sdram/nll0lO/\g_datapath:1

                               
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_ddr_io /dm_pin
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'hrbypass'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'oe_out'.
# ** Warning: (vsim-3017) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Too few port connections. Expected 12, found 8.
#         Region: /ddr2_top_tb/dut/ddr2_ctrl_ddr_sdram/nll0lO/\g_datapath:2

                               
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_ddr_io /dm_pin
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'hrbypass'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'oe_out'.
# ** Warning: (vsim-3017) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Too few port connections. Expected 12, found 8.
#         Region: /ddr2_top_tb/dut/ddr2_ctrl_ddr_sdram/nll0lO/\g_datapath:3

                               
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_ddr_io /dm_pin
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'hrbypass'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'oe_out'.
# ** Warning: (vsim-3017) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Too few port connections. Expected 12, found 8.
#         Region: /ddr2_top_tb/dut/ddr2_ctrl_ddr_sdram/nll0lO/\g_datapath:4

                               
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_ddr_io /dm_pin
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'hrbypass'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'oe_out'.
# ** Warning: (vsim-3017) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Too few port connections. Expected 12, found 8.
#         Region: /ddr2_top_tb/dut/ddr2_ctrl_ddr_sdram/nll0lO/\g_datapath:5:g_ddr_io /dm_pin
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'hrbypass'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'oe_out'.
# ** Warning: (vsim-3017) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Too few port connections. Expected 12, found 8.
#         Region: /ddr2_top_tb/dut/ddr2_ctrl_ddr_sdram/nll0lO/\g_datapath:6:g_ddr_io /dm_pin
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'hrbypass'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'oe_out'.
# ** Warning: (vsim-3017) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Too few port connections. Expected 12, found 8.
#         Region: /ddr2_top_tb/dut/ddr2_ctrl_ddr_sdram/nll0lO/\g_datapath:7:g_ddr_io /dm_pin
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sset'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'sclr'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'hrbypass'.
# ** Warning: (vsim-3722) ../../ddr2_ctrl_auk_ddr_dqs_group.v(182): [TFMPC] - Missing connection for port 'oe_out'.
# ** Warning: (vsim-3017) ../../ddr2_top.v(237): [TFMPC] - Too few port connections. Expected 19, found 18.
#         Region: /ddr2_top_tb/dut/driver
# ** Warning: (vsim-3722) ../../ddr2_top.v(237): [TFMPC] - Missing connection for port 'burst_begin'.
# ** Warning: (vsim-3017) ../ddr2_top_tb.v(245): [TFMPC] - Too few port connections. Expected 18, found 16.
#         Region: /ddr2_top_tb/ddr2_module_inst
# ** Warning: (vsim-3015) ../ddr2_top_tb.v(245): [PCDPC] - Port size (3 or 3) does not match connection size (1) for port 'ck'. The port definition is at: ../ddr2_module.v(47).
#         Region: /ddr2_top_tb/ddr2_module_inst
# ** Warning: (vsim-3015) ../ddr2_top_tb.v(245): [PCDPC] - Port size (3 or 3) does not match connection size (1) for port 'ck_n'. The port definition is at: ../ddr2_module.v(48).
#         Region: /ddr2_top_tb/ddr2_module_inst
# ** Warning: (vsim-3015) ../ddr2_top_tb.v(245): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 'cke'. The port definition is at: ../ddr2_module.v(49).
#         Region: /ddr2_top_tb/ddr2_module_inst
# ** Warning: (vsim-3015) ../ddr2_top_tb.v(245): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 's_n'. The port definition is at: ../ddr2_module.v(50).
#         Region: /ddr2_top_tb/ddr2_module_inst
# ** Warning: (vsim-3015) ../ddr2_top_tb.v(245): [PCDPC] - Port size (16 or 16) does not match connection size (14) for port 'addr'. The port definition is at: ../ddr2_module.v(55).
#         Region: /ddr2_top_tb/ddr2_module_inst
# ** Warning: (vsim-3015) ../ddr2_top_tb.v(245): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port 'odt'. The port definition is at: ../ddr2_module.v(56).
#         Region: /ddr2_top_tb/ddr2_module_inst
# ** Warning: (vsim-3015) ../ddr2_top_tb.v(245): [PCDPC] - Port size (18 or 18) does not match connection size (8) for port 'dqs'. The port definition is at: ../ddr2_module.v(57).
#         Region: /ddr2_top_tb/ddr2_module_inst
# ** Warning: (vsim-3722) ../ddr2_top_tb.v(245): [TFMPC] - Missing connection for port 'reset_n'.
# ** Warning: (vsim-3722) ../ddr2_top_tb.v(245): [TFMPC] - Missing connection for port 'cb'.
# Note: DLL instance ddr2_top_tb.dut.dll.dll has input frequency 6667 ps
#       sim_valid_lock 1
#       sim_valid_lockcount 27
#       sim_loop_intrinsic_delay 3600
#       sim_loop_delay_increment 144
#       delay_buffer_mode low
#       delayctrlout_mode normal
#       static_delay_ctrl 0
#       offsetctrlout_mode dynamic_addnsub
#       static_offset 0
#       use_jitter_reduction false
#       use_upndnin false
#       use_upndninclkena false
# ddr2_top_tb.ddr2_module_inst: Single Rank
# ddr2_top_tb.ddr2_module_inst: non ECC
# ddr2_top_tb.ddr2_module_inst: UDIMM
# ddr2_top_tb.ddr2_module_inst: Component Width = x16
#  Note : Stratix II GX PLL is enabled
# Time: 0.0 ps  Instance: ddr2_top_tb.dut.g_stratixpll_ddr_pll_inst.altpll_component.stratixii_pll.pll1
# Warning : Invalid transition to 'X' detected on StratixII PLL input clk. This edge will be ignored.
# Time: 0.0 ps  Instance: ddr2_top_tb.dut.g_stratixpll_ddr_pll_inst.altpll_component.stratixii_pll.pll1.n1
#  Note : Stratix II GX PLL was reset
# Time: 0.0 ps  Instance: ddr2_top_tb.dut.g_stratixpll_ddr_pll_inst.altpll_component.stratixii_pll.pll1
#                43329  Note : DLL instance ddr2_top_tb.dut.dll.dll to lock to incoming clock per sim_valid_lock half clock cycles.
#                45551  Warning : Duty Cycle violation DLL instance ddr2_top_tb.dut.dll.dll. Specified duty cycle is 3333 ps but actual is 2222 ps
#                47773  Warning : Input frequency violation on DLL instance ddr2_top_tb.dut.dll.dll. Specified input period is 6667 ps but actual is 4444 ps
#  Note : Stratix II GX PLL locked to incoming clock
# Time: 49995.0 ps  Instance: ddr2_top_tb.dut.g_stratixpll_ddr_pll_inst.altpll_component.stratixii_pll.pll1

...
...


# Break in NamedBeginStat endit at ../ddr2_top_tb.v line 509
           140538167          --- SIMULATION FAILED ---

这个的是由什么原因引起的，请高手帮忙，感谢！！

wangyingwei

DQ及DQS有输出并不一定就表示写进去了，要先激活地址，等待RCD时间，执行写操作，再等WL时间的数据才算写进去。若楼主对协议不熟，建议把美光的模型的DEBUG功能打开，也可以判断是否成功写入

sgx7448350

回复 2# wangyingwei
这个逻辑我在硬件上已经测试过了，从DDR2中读出的数与写入的相同，时序的问题应该满足吧。现在就是想做一下仿真，但是仿真不对...

digitalimage

你仔细看看这2条warning，明显给的高了，DLL根本锁不住，看看你给的时钟是不是和model匹配?
#45551  Warning : Duty Cycle violation DLL instance ddr2_top_tb.dut.dll.dll. Specified duty cycle is 3333 ps but actual is 2222 ps
#                47773  Warning : Input frequency violation on DLL instance ddr2_top_tb.dut.dll.dll. Specified input period is 6667 ps but actual is 4444 ps