回复 3# 子幽墨雨
Generally speaking, there is not the best ones. All the verification methodologies are developed by simulator suppliers and verification languages and are commercial. They just compete with each other to earn more marketplaces. But the fierce compete leads to progress of the whole EDA industry, there do have step a big forward. Say, it much like weapons, are you sure the more complicated ones can beat all enemies？the answer maybe no. The more complicated the more difficult to master, you have to spend much time to learn the language and methodology, also you must gain enough experience before you can use it powerfully. In my opinion, one should choose the easiest way to handle problems, the easiest is the best, not the most complicated ones. If your project is small like AVS decoder, you may not need to apply the more advanced methodologies, verilog is just enough to deal all things, maybe some other verification languages also will do,such as E,Vera.If your project really very big, such as smart phones SOC etc. verilog is inefficient to take charge in, then, you may think of more advanced methodologies, such as OVM, VMM, UVM. they will make verification easier. the other choice when one face to SOC era, one may use the powerful SystemC as a system model and verification tools. the more abstract the more one can improve their productivity and efficiency.
So dude, I'm glad you are interested in UVM, but use it carefully before you think clearly. Good luck! |
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2012-3-26 15:04:30
楼主
