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CONTENT
2011_JSSC_ADC1:
A 0.6-V 82-dB 28.6- W Continuous-Time Audio Delta-Sigma Modulator.pdf
A 0.8-mW 5-bit 250-MSs Time-Interleaved Asynchronous Digital Slope ADC.pdf
A 2.4 GSs, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS.pdf
A 4 GHz Continuous-Time $DeltaSigma$ ADC With 70 dB DR and $-$74 dBFS THD in 125 MHz BW.pdf
A 10-bit, 40-MSs, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bitcycle Conversion Technique.pdf
A 12-Bit 1.25-GSs DAC in 90 nm CMOS With 70 dB SFDR up to 500 MHz.pdf
A 12-bit, 45-MSs, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration.pdf
A 12-GSs 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration.pdf
A 14 bit 200 MSs DAC With SFDR 78 dBc, IM3 83 dBc and NSD 163 dBmHz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping.pdf
2011_JSSC_ADC1.rar
(13.77 MB, 下载次数: 1661 )
2011_JSSC_ADC2:
A 21 fJConversion-Step 100 kSs 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface.pdf
A 26 W 8 bit 10 MSs Asynchronous SAR ADC for Low Energy Radios.pdf
A 480 mW 2.6 GSs 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS.pdf
A 550- 10-b 40-MSs SAR ADC With Multistep Addition-Only Digital Error Correction.pdf
A CMOS 6-Bit 16-GSs Time-Interleaved ADC Using Digital Background Calibration Techniques.pdf
A Continuous Time Multi-Bit ADC Using Time Domain Quantizer and Feedback Element.pdf
A Digitally Corrected 5-mW 2-MSs SC $DeltaSigma$ ADC in 0.25- $mu$m CMOS With 94-dB SFDR.pdf
A SAR-Assisted Two-Stage Pipeline ADC.pdf
A Third-Order DT $DeltaSigma$ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer.pdf
An 8.5 mW Continuous-Time $Delta Sigma $ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR.pdf
An 800 MSs Dual-Residue Pipeline ADC in 40 nm CMOS.pdf
2011_JSSC_ADC2.rar
(13.27 MB, 下载次数: 1501 )
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发表于 2011-12-10 03:03:19
