请教这个程序主要是实现什么功能的啊

summuy · 发表于 2011-11-25 12:10:35

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本帖最后由 summuy 于 2011-11-25 15:02 编辑

仿真的波形图

module dso_sinc_mult(clk,reset, x_in,datain,endata_out,sum);

/*y_out1,y_out2,y_out3,y_out4,y_out5,y_out6,y_out7,y_out8,y_out9,y_out10,*/

input clk,reset;
input signed [7:0] x_in;
input signed [7:0] datain;

output  signed [16:0] sum;
output endata_out;

//output  signed [16:0] y_out1,y_out2,y_out3,y_out4,y_out5,y_out6,y_out7,y_out8,y_out9,y_out10;
//reg signed [16:0] y_out1,y_out2,y_out3,y_out4,y_out5,y_out6,y_out7,y_out8,y_out9,y_out10;

reg [4:0] count;
reg    endata_out ;//, ena_io
reg    signed [16:0] dataout; // temp sum
reg    signed [7:0]  ibuf [0:10];
reg    signed [16:0] sum; // temp sum
parameter          IL = 9;

/////////////////////////////////////////////////////////////////////////////

always @(posedge reset or posedge clk)
  begin : FSM  // Control the system and sample at clk rate
if (reset)             // Asynchronous reset
   count <=5'b0;
else begin
   if (count ==5'b10011)
      count <=5'b0;
   else
      count <= count +5'b1;
end
  end
/*always @(posedge clk)
begin
if (count == 0)
      ena_io <= 1;
   else
      ena_io <= 0;
  end*/

  always @(posedge clk)
  begin       // set the enable signal for the TAP lines
   case (count)
   1,3,5,7,9,11,13,15,17,19: endata_out <= 1;
      default : endata_out <= 0;
   endcase

end

always @(posedge clk)
  begin :  INPUTMUX
  integer I;
   begin
      ibuf[0] <= x_in;
         for (I=0; I<=IL; I=I+1)
            ibuf[I+1] <= ibuf[I];

   end
  end

///////////**************************************************************/////////////
always @(posedge clk) // Compute sum-of-products for f0
  begin :  OUPUTMUX
reg    signed [16:0] p [0:9];
integer I;
begin
   dataout = p[0];
   for (I=0; I<=IL; I=I+1) // Infer L+1  multiplier
            begin
            p[I] = ibuf[I]*datain  ;
            dataout= dataout + p[I];
            sum  <=  dataout ;
            end
end
end
//******************************************************************************************//

endmodule