|
发表于 2011-10-12 05:48:27
|
显示全部楼层
//This is a dual-edge detector based on mealy FSM
module detector
(
input wire clk, reset,
input wire level,
output reg tick
);
localparam zero = 1'b0,
one = 1'b1;
reg state_reg, state_next;
always @(posedge clk, posedge reset)
begin
if (reset)
state_reg <= zero;
else
state_reg <= state_next;
end
always @*
begin
state_next = state_reg;
tick = 1'b0;
case (state_reg)
zero:
begin
if (level)
begin
state_next = one;
tick = 1'b1;
end
end
one:
begin
if (!level)
begin
state_next = zero;
tick = 1'b1;
end
end
default: state_next = zero;
endcase
end
endmodule |
|