A CMOS PRECISION VOLTAGE REFERENCE IC

smithpwb

虽然是学士学位论文，个人觉得值得一看，因为它把做基准的整个过程都讲到了。
A CMOS PRECISION VOLTAGE REFERENCE IC





LIST OF FIGURES AND TABLES .......................................................................................................4
1 INTRODUCTION.........................................................................................................................6
1.1 GOALS........................................................................................................................................6
1.2 ABOUT ALLEGRO MICROSYSTEMS ................................................................................................7
1.3 THE MAJOR QUALIFYING PROJECT (MQP) ....................................................................................7
2 LITERATURE REVIEW..............................................................................................................8
2.1 VOLTAGE REFERENCES ................................................................................................................8
2.1.1 Zener References................................................................................................................9
2.1.2 Bandgap References .........................................................................................................10
2.2 METHODS OF TEMPERATURE STABILIZATION ..............................................................................12
2.2.1 Basic Bandgap Reference .................................................................................................13
2.2.2 Brokaw Reference ............................................................................................................14
2.2.3 Curvature Correction .......................................................................................................17
2.3 METHODS OF ADJUSTING AND TRIMMING RESISTORS ..................................................................18
2.3.1 Abrasive Trimming...........................................................................................................19
2.3.2 Laser Trimming................................................................................................................20
2.3.3 Link Fuse Trimming .........................................................................................................25
2.3.4 Circuit Adjusting with Potentiometers...............................................................................27
2.3.5 Using Zener Diode Sets for Adjustments ...........................................................................27
2.3.6 Electronically Programmable Analog Devices ..................................................................27
2.3.7 Comparison of Different Trimming Techniques .................................................................29
3 METHODOLOGY......................................................................................................................33
3.1 DEVELOPING A BACKGROUND ....................................................................................................33
3.2 DESIGN OF THE INTEGRATED CIRCUIT .........................................................................................34
3.2.1 Desired Specifications ......................................................................................................34
3.2.2 Choosing a Design Model (Brokaw vs. Widlar).................................................................34
3.2.3 Choosing Design Layout Tools .........................................................................................35
3.2.4 Choosing a Fabrication Process .......................................................................................35
3.2.5 Trimming Technique.........................................................................................................36
3.3 SIMULATING AND TESTING OUR DESIGN.....................................................................................37
3.4 COMPLETION OF THE PROJECT ....................................................................................................37
4 DESIGN ......................................................................................................................................39
4.1 THE BROKAW CELL AND THE BANDGAP VOLTAGE ......................................................................40
4.2 AMI 1.2m PROCESS ....................................................................................................................41
4.3 BJT MODELS .............................................................................................................................42
4.3.1 Diode Connected Transistors............................................................................................42
4.3.2 NPN Transistors in a CMOS Process................................................................................43
4.3.3 PNP Transistor in a CMOS Process .................................................................................44
4.3.4 Saturation Currents..........................................................................................................46
4.4 CURRENT SETTING TRANSISTORS................................................................................................47
4.4.1 Primary Current Source ...................................................................................................47
4.4.2 Startup Circuit .................................................................................................................47
4.5 OPERATIONAL TRANSCONDUCTANCE AMPLIFIER ........................................................................48
4.5.1 Input Offset Voltage..........................................................................................................49
4.5.2 PMOS Current Source......................................................................................................50
4.5.3 Differential Pair...............................................................................................................50
4.5.4 Active loads......................................................................................................................50
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4.5.5 Biasing............................................................................................................................51
4.5.6 More Current Sources ......................................................................................................51
4.5.7 Capacitor Compensation ..................................................................................................51
4.5.8 Cascoded Output ..............................................................................................................53
4.5.9 Inverting and Non-Inverting Terminals .............................................................................54
4.5.10 Specifications of the Amplifier ..........................................................................................55
4.6 DESIGN OF POLY RESISTORS.......................................................................................................59
4.6.1 Absolute Error in Resistors Due to Process Variations......................................................59
4.6.2 Resistor Values.................................................................................................................60
4.6.3 Initial Accuracy................................................................................................................61
4.7 TRIM RESISTOR CONSIDERATIONS ..............................................................................................63
4.8 NON-INVERTING GAIN AMPLIFIER...............................................................................................67
4.8.1 Amplifier Modifications ....................................................................................................67
4.8.2 Gain Setting .....................................................................................................................69
4.9 FINAL LAYOUT ..........................................................................................................................69
4.9.1 Test Structures .................................................................................................................70
4.9.2 Bandgap Circuit ...............................................................................................................70
4.9.3 Pin Assignments ...............................................................................................................72
5 TRIM SCHEME PROCEDURE .................................................................................................77
5.1 DEVELOPING THE TRIM PROCEDURE ...........................................................................................77
5.2 ACTUAL TRIM PROCEDURE.........................................................................................................79
6 TEST PROCEDURE ...................................................................................................................85
6.1 DESIGNING THE PC BOARD ........................................................................................................85
6.2 ACTUAL TEST PROCEDURE .........................................................................................................86
7 TEST RESULTS.........................................................................................................................89
7.1 TEST PREPARATION....................................................................................................................90
7.2 NPN TEST ................................................................................................................................91
7.3 PNP TEST.................................................................................................................................94
7.4 AMPLIFIER TEST RESULTS ..........................................................................................................98
7.5 PROBLEMS WITH PROBE STATION FUNCTIONALITY....................................................................100
7.6 TEST CIRCUIT #3 (PNP) ...........................................................................................................100
7.6.1 Trimming VBANDGAP to 1.25 .............................................................................................101
7.6.2 Voltage Supply Sweep.....................................................................................................104
7.7 TEST CIRCUIT #2 (NPN)...........................................................................................................105
7.8 MEASURE TRIM RESISTOR........................................................................................................107
8 CONCLUSIONS AND RECOMMENDATIONS .....................................................................108
8.1 OVERALL DESIGN ....................................................................................................................108
8.2 TRANSISTORS IN A CMOS PROCESS..........................................................................................109
8.3 AMPLIFIER..............................................................................................................................109
8.4 TRIMMING ...............................................................................................................................110
8.5 TRIMMING CONSIDERATION......................................................................................................110
8.6 RECOMMENDATION FOR START UP CIRCUIT ..............................................................................110
REFERENCES...................................................................................................................................111
APPENDIX A: DIE PHOTOS............................................................................................................113
APPENDIX B: GLOSSARY AND ACRONYMS...............................................................................118
APPENDIX C: FUNDAMENTAL PRINCIPLES OF BIPOLAR JUNCTION TRANSISTORS.....119

pedro888

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fanjx

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fanjx

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semico_ljj

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ct511ct

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sfchen1969

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