A 40-MS/s SAR ADC with Digital Error Correction

angelweishan · 发表于 2011-7-15 16:53:04

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本帖最后由 angelweishan 于 2011-7-15 17:19 编辑

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 2011 1

A 550uW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction

Sang-Hyun Cho, Student Member, IEEE, Chang-Kyo Lee, Student Member, IEEE, Jong-Kee Kwon, Member, IEEE,
and Seung-Tak Ryu, Member, IEEE

Abstract—A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible hardware overhead. The redundant decision cycles between stages reconfigure the capacitor connection of the DAC. These redundancies guarantee 10-b linearity under 4-b-accurate DAC settling in the MSB decision and the optimally designed ADC enhances the conversion speed by 37%. A prototype ADC was implemented in a CMOS 0.13- m technology. The chip consumes 550 W and achieves a 50.6-dB SNDR at 40 MS/s under a 1.2-V supply. The figure-of-merit (FOM) is 50 fJ/conversion-step. Index Terms—Addition-only digital error correction (ADEC), asynchronous, digital error correction, multistep binary error correction, SAR ADC.

alan194 · 发表于 2011-7-15 21:17:02

thanks

hezudao · 发表于 2011-7-16 00:58:50

seems not published yet

scu01 · 发表于 2011-7-31 10:00:56

xie xie

vensen · 发表于 2011-7-31 10:29:34

谢谢共享

semico_ljj · 发表于 2011-7-31 11:29:41

good...

goat_xdg · 发表于 2011-8-8 13:57:48

回复 1# angelweishan

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黎明清风 · 发表于 2011-9-5 11:50:47

Good,thank for share !!

lpf025 · 发表于 2011-9-18 20:28:27

hao duoxie LZ LE

hitpiano · 发表于 2011-10-6 18:47:40

rerere

[资料] A 40-MS/s SAR ADC with Digital Error Correction

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