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楼主 |
发表于 2011-3-4 17:47:48
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回复 3# jackertja
component float_divide
port (
a: IN std_logic_VECTOR(31 downto 0);
b: IN std_logic_VECTOR(31 downto 0);
operation_nd: IN std_logic;
operation_rfd: OUT std_logic;
clk: IN std_logic;
sclr: IN std_logic;
ce: IN std_logic;
result: OUT std_logic_VECTOR(31 downto 0);
rdy: OUT std_logic);
end component;
tofudian1 : float_divide
port map (
a => shuju1_d,
b => shuju2_d,
operation_nd => op_nd_d,
operation_rfd => op_rfd_d,
clk => clk,
sclr => sclr_d,
ce => ce_d,
result => feng_fudian_60,
rdy => ready_d);
process(ok_fd)
begin
if ok_fd='1' then
ce_d<='1';
else
ce_d<='0';
end if;
end process;
process(clk,ce_d)
begin
if ce_d='1' then
if clk'event and clk='1' then
if count_d="10" then
count_d<="10";
else
count_d<=count_d+'1';
end if;
end if;
end if;
end process;
process(count_d)
begin
if count_d="01" then
sclr_d<='1';
else
sclr_d<='0';
end if;
end process;
process(op_rfd_d)
begin
if op_rfd_d'event and op_rfd_d='1' then
shuju1_d<=xiaoshu_fudian;
shuju2_d<=liushi;
op_nd_d<='1';
end if;
end process;
process(ready_d)
begin
if ready_d='1' then
ce_a<='1';
else
ce_a<='0';
end if;
end process;
process(ce_a,clk)
begin
if ce_a='1' then
if clk'event and clk='1' then
if count_a="10" then
count_a<="10";
else
count_a<=count_a+'1';
end if;
end if;
end if;
end process;
process(count_a)
begin
if count_a="01" then
sclr_a<='1';
else
sclr_a<='0';
end if;
end process;
process(op_rfd_a)
begin
if op_rfd_a'event and op_rfd_a='1' then
shuju1_a<=feng_fudian_60;
shuju2_a<=du_fudian;
op_nd_a<='1';
end if;
end process;
这是用浮点核做除法中的几段代码,还请指点一二。 |
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