最新：<<The Power of Assertions in SystemVerilog >>

wilfred · 发表于 2011-1-13 10:30:07

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Power of Assertions in SystemVerilog.pdf (3.46 MB, 下载次数: 463 )

Publisher: Springer | 2010 | PDF | 544 pages

This book provides a deeper understanding of the meaning of the enhancements contained in the new SystemVerilog 1800-2009 LRM. In particular, it discusses the context of practical deployment in hardware design projects. The material also addresses language implementation alternatives and their impact on simulation performance as well as the ability to debug them in simulation and formal verification environments. The underlying performance issues are illustrated for practical examples drawn from the author's experience.

Daniel10003 · 发表于 2011-1-13 11:09:23

呵呵，谢谢楼主

mtwumtwu · 发表于 2011-1-13 11:39:36

good reference for power control

luren2011 · 发表于 2011-1-13 14:21:00

thansk

QK168 · 发表于 2011-1-13 14:21:16

try run

zh123456789 · 发表于 2011-1-13 23:09:49

已经有人发过了

alexpanait · 发表于 2011-1-14 03:29:53

thanks, thanks and thanks.

suibianle · 发表于 2011-1-14 11:52:04

回复 1# wilfred

ding lou zhu

javasun · 发表于 2011-12-16 10:50:19

很好的材料

xcykii · 发表于 2012-3-8 20:24:38

很好的材料

[资料] 最新：<<The Power of Assertions in SystemVerilog >>

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