请问高手 verilog 循环要如何写才能通过综合编译？

melinda

有如下程序
for(count=0;count<=254;count=count+1)
  begin   
   while(n<16)
   begin
    for(j=0;j<3;j=j+1)
      begin
      FD[n] <= fromFIFO1[j];
      n = n + 1;
      end
   end
   n = 0;
end

编译错误是：
Error (10106): Verilog HDL Loop error at usb.v(177): loop must terminate within 5000 iterations

5000次不是远远没有超过吗？请问问题如在哪里呢？好像每次一用while就会出问题！
请高手赐教呀！非常感谢！！

melinda

问题补充：
  编译此程序的小模块是没有错误，成功了；
  在编译整个工程时才出现上面所说的错误。

谢谢！

zh123456789

每次n=0，循环怎么结束啊

stephua

楼上的signature不错。

achillowy

你嵌套了太多次了吧？
3x16x255=12240  早超过了

melinda

回复 3# zh123456789


    n=0 是在while之后。

melinda

回复 5# achillowy


    n在for循环里面增加的。一共是254*16=4080。

melinda

楼上的signature不错。
stephua 发表于 2010-12-8 15:54

                               
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    能再看看吗？

stephua

你在整个编译的时候把这里面的参数调小一些，试试看能不能通过编译。

你说你单个小模块能编译，大工程编译就通不过，是不是编译器对FOR循环的次数是累加来计算的，所有的加起来不能过5K？个人没用过FOR，对这个不大清楚

melinda

你在整个编译的时候把这里面的参数调小一些，试试看能不能通过编译。

你说你单个小模块能编译，大工程编 ...
stephua 发表于 2010-12-8 17:27

                               
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    谢谢你的提示。好像嵌套的循环总是不行的。改了一下就好了：
把最里层的for循环改成：
     FD[n] <= fromFIFO1[0];
     FD[n+1] <= fromFIFO1[1];
     FD[n+2] <= fromFIFO1[2];
     n = n + 3;

不知道我的做法是否高效，但是现在能通过综合编译了。但警告还是很多呀！不知道哪位能看看不？

Warning (10272): Verilog HDL Case Statement warning at autoshift.v(29): case item expression covers a value already covered by a previous case item
Warning (10235): Verilog HDL Always Construct warning at usb.v(66): variable "SLWR" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(67): variable "SLWR" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(71): variable "SLRD" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(79): variable "SLRD" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10272): Verilog HDL Case Statement warning at usb.v(78): case item expression covers a value already covered by a previous case item
Warning (10230): Verilog HDL assignment warning at usb.v(101): truncated value with size 32 to match size of target (8)
Warning (10235): Verilog HDL Always Construct warning at usb.v(117): variable "FD" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at usb.v(116): truncated value with size 32 to match size of target (8)
Warning (10235): Verilog HDL Always Construct warning at usb.v(139): variable "fromFIFO0" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at usb.v(138): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at usb.v(163): truncated value with size 10 to match size of target (8)
Warning (10235): Verilog HDL Always Construct warning at usb.v(173): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(175): variable "fromFIFO1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(175): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(176): variable "fromFIFO1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(176): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(177): variable "fromFIFO1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(177): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(178): variable "i" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at usb.v(178): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at usb.v(171): truncated value with size 32 to match size of target (8)
Warning (10272): Verilog HDL Case Statement warning at usb.v(166): case item expression covers a value already covered by a previous case item
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "EP2FULL", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "FIFOADR", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "SLWR", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "SLRD", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "wrreq1", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "toFIFO1", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "rdreq0", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "FD", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "EP6EMPT", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "ad_cs", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "SLOE", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "wrreq0", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "PKEND", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "rdreq1", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(85): inferring latch(es) for variable "i", which holds its previous value in one or more paths through the always construct
Warning: Using design file altpll0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: altpll0
Warning: Using design file fifo1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: fifo1
Warning: LATCH primitive "USB:inst5|i" is permanently disabled
Warning: The following nodes have both tri-state and non-tri-state drivers
Warning: Inserted always-enabled tri-state buffer between "FD[11]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[10]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[9]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[8]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[7]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[6]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[5]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[4]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[3]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[2]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[1]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[0]" and its non-tri-state driver.
Warning: The following tri-state nodes are fed by constants
Warning: The pin "FD[15]" is fed by GND
Warning: The pin "FD[14]" is fed by GND
Warning: The pin "FD[13]" is fed by GND
Warning: The pin "FD[12]" is fed by GND
Warning: TRI or OPNDRN buffers permanently enabled
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "da_cs" is stuck at VCC
Warning (13410): Pin "da_wr" is stuck at VCC
Warning (13410): Pin "full" is stuck at VCC
Warning (13410): Pin "empty" is stuck at GND
Warning (13410): Pin "PKEND" is stuck at GND
Warning (13410): Pin "SLOE" is stuck at GND
Warning (13410): Pin "da_in[7]" is stuck at VCC
Warning (13410): Pin "da_in[6]" is stuck at VCC
Warning (13410): Pin "da_in[5]" is stuck at VCC
Warning (13410): Pin "da_in[4]" is stuck at VCC
Warning (13410): Pin "da_in[0]" is stuck at GND
Warning (13410): Pin "FIFOADR[0]" is stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "msb"
Warning: Ignored locations or region assignments to the following nodes
Warning: Node "IFCLK" is assigned to location or region, but does not exist in design
Warning: Node "ad_clk" is assigned to location or region, but does not exist in design
Warning: Node "sht[0]" is assigned to location or region, but does not exist in design
Warning: Node "sht[1]" is assigned to location or region, but does not exist in design
Warning: Node "sht[2]" is assigned to location or region, but does not exist in design
Warning: Node "sht[3]" is assigned to location or region, but does not exist in design
Warning: Found 39 output pins without output pin load capacitance assignment
Info: Pin "FD[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_cs" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_wr" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "full" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "empty" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "PKEND" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "SLWR" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "SLRD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "SLOE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "EP6EMPT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "EP2FULL" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FIFOADR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FIFOADR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "multi_in[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "multi_in[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "multi_in[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning: Following 16 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
Info: Pin FD[15] has a permanently enabled output enable
Info: Pin FD[14] has a permanently enabled output enable
Info: Pin FD[13] has a permanently enabled output enable
Info: Pin FD[12] has a permanently enabled output enable
Info: Pin FD[11] has a permanently enabled output enable
Info: Pin FD[10] has a permanently enabled output enable
Info: Pin FD[9] has a permanently enabled output enable
Info: Pin FD[8] has a permanently enabled output enable
Info: Pin FD[7] has a permanently enabled output enable
Info: Pin FD[6] has a permanently enabled output enable
Info: Pin FD[5] has a permanently enabled output enable
Info: Pin FD[4] has a permanently enabled output enable
Info: Pin FD[3] has a permanently enabled output enable
Info: Pin FD[2] has a permanently enabled output enable
Info: Pin FD[1] has a permanently enabled output enable
Info: Pin FD[0] has a permanently enabled output enable
Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "USB:inst5|toFIFO1[0]" is a latch
Warning: Node "USB:inst5|toFIFO1[1]" is a latch
Warning: Node "USB:inst5|toFIFO1[2]" is a latch
Warning: Node "USB:inst5|toFIFO1[3]" is a latch
Warning: Node "USB:inst5|FD[0]$latch" is a latch
Warning: Node "USB:inst5|FD[1]$latch" is a latch
Warning: Node "USB:inst5|FD[2]$latch" is a latch
Warning: Node "USB:inst5|FD[3]$latch" is a latch
Warning: Node "USB:inst5|EP2FULL" is a latch
Warning: Node "USB:inst5|SLRD" is a latch
Warning: Node "USB:inst5|EP6EMPT" is a latch
Warning: Node "USB:inst5|SLWR" is a latch
Warning: Node "USB:inst5|FD[11]$latch" is a latch
Warning: Node "USB:inst5|FD[10]$latch" is a latch
Warning: Node "USB:inst5|FD[9]$latch" is a latch
Warning: Node "USB:inst5|FD[8]$latch" is a latch
Warning: Node "USB:inst5|FD[7]$latch" is a latch
Warning: Node "USB:inst5|FD[6]$latch" is a latch
Warning: Node "USB:inst5|FD[5]$latch" is a latch
Warning: Node "USB:inst5|FD[4]$latch" is a latch
Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "USB:inst5|always2~3" as buffer
Info: Detected gated clock "USB:inst5|WideOr0" as buffer
Info: Detected ripple clock "USB:inst5|state.state3" as buffer
Info: Detected ripple clock "USB:inst5|state.state0" as buffer
Info: Detected ripple clock "USB:inst5|state.state2" as buffer
Info: Detected ripple clock "USB:inst5|state.state1" as buffer
Warning: Can't achieve minimum setup and hold requirement altpll0:inst8|altpll:altpll_component|_clk0 along 2 path(s). See Report window for details.