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本帖最后由 helianalog 于 2011-1-30 09:26 编辑
经过较长时间的泡坛我发现，好多人都在发帖寻求JSSC论文。如果大家需要的话，我考虑把2000-2010年的JSSC论文发上来，也算是对论坛作一点贡献。我现把2010年JSSC合集（1-11月）发上来（后面持续更新），看大家的反响如何，大家的支持就是我最大的动力^_^
PS：由于小弟我是学生，每天不能下载太多论文，要不然很可能会被学校发现而受处分，所以我是冒着风险这么做的，还望大家能够理解。当然，我会尽最大努力完成并做好这件事，前提是如果大家需要的话。另外，有谁急着需要一些论文的话，可以短消息我，我会尽力帮你下载。最后，还请大家在下载时别忘顶下贴 
以下是2010年合集（1-11月）。按每期（一月一期）分类发布，每期的内容列表放在压缩包前面，方便大家查阅。
Issue 1
1.Introduction to the Special Issue on the 2009 IEEE International Solid-State Circuits Conference
2.A 45 nm 8-Core Enterprise Xeon Processor
3.A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors
4.Securing Encryption Systems With a Switched Capacitor Current Equalizer
5.A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine
6.A 212 MPixels/s 4096 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications
7.A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits
8.A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging
9.A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit
10.A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS
11.A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management
12.8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
13.A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques
14.2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking
15.A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes
16.A Pulsed UWB Receiver SoC for Insect Motion Control
17.A Bulk Acoustic Wave (BAW) Based Transceiver for an In-Tire-Pressure Monitoring Sensor Node
18.A 5.2 mW Self-Configured Wearable Body Sensor Network Controller and a 12 W Wirelessly Powered Sensor for a Continuous Health Monitoring System
19.An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Bias-Flip Rectifier and Shared Inductor
20.An Integrated Power Supply System for Low Power 3.3 V Electronics Using On-Chip Polymer Electrolyte Membrane (PEM) Fuel Cells
21.A GHz Spintronic-Based RF Oscillator
22.Silicon Resonator Based 3.2 W Real Time Clock With 10 ppm Frequency Accuracy
23.Optical I/O Technology for Tera-Scale Computing
24.Stretchable EMI Measurement Sheet With 8 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 m Silicon CMOS LSIs for Electric and Magnetic Field Detection
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Issue 1.part09.rar
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Issue 1.part10.rar
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Issue 1.part11.rar
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Issue 1.part12.rar
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Issue 2
1.A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly
2.Software Assisted Digital RF Processor (DRP) for Single-Chip GSM Radio in 90 nm CMOS
3.A Millimeter-Wave (23–32 GHz) Wideband BiCMOS Low-Noise Amplifier
4.An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC
5.A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO
6.Dynamic Quadrant Swapping Scheme Implemented in a Post Conversion Block for I, Q Mismatch Reduction in a DQPSK Receiver
7.A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband
8.Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications
9.LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta-Sigma Modulators
10.A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology
11.An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18um CMOS
12.Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation
13.A 74.8 mW Soft-Output Detector IC for 8x8 Spatial-Multiplexing MIMO Communications
14.Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture
15.A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers
16.Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects
17.An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection
18.Switch-Matrix-Based High-Density Microelectrode Array in CMOS Technology
19.A 0.7 um BiCMOS Electrostatic Energy-Harvesting System IC
20.Correction on “A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme” [Aug 09 2222-2232]
21.Correction to “Baseband and Audio Mixed-Signal Front-End IC for GSM or EDGE Applications” [Jun 06 1364-1379]
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Issue 3
1.A Compact Wideband CMOS Low Noise Amplifier With Gain Flatness Enhancement
2.A Current Reuse Quadrature GPS Receiver in 0.13um CMOS
3.5–10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS
4.A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications
5.A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply
6.High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique
7.A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology
8.A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders
9.A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of ?0.4°C ～ +0.6°C Over a 0°C to 90°C Range
10.A 0.02-mm 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology
11.A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp
12.An 80 mW 40 Gb/s 7-Tap 0.5T-Spaced Feed-Forward Equalizer in 65 nm CMOS
13.All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits
14.A 116 fps/74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications
15.An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage
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Issue 4
1.Introduction to the Special Issue on the 2009 Symposium on VLSI Circuits
2.A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator
3.A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture
4.Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC
5.A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
6.A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting
7.Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process
8.A 0.5 V Sub-Microwatt CMOS Image Sensor With Pulse-Width Modulation Read-Out
9.A Fractional-N PLL for Multiband (0.8–6 GHz) Communications Using Binary-Weighted D/A Differentiator and Offset-Frequency Δ-Σ Modulator
10.A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology
11.187 MHz Subthreshold-Supply Charge-Recovery FIR
12.A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System
13.An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB
14.A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 $mu{hbox {m}}$ CMOS Technology
15.An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors
16.3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link
17.A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 $mu$ m$^{2}$ 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS
18.A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme
19.A 31 ns Random Cycle VCAT-Based 4F $^{2}$ DRAM With Manufacturability and Enhanced Cell Efficiency
20.A 4.3 GB pre s Mobile Memory Interface With Power-Efficient Bandwidth Scaling
21.A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS
22.A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology
23.A 0.2 mm$^{2}$ , 27 Mbps 3 mW ADC/FFT-Less FDM BAN Receiver With Energy Exploitation Capability
24.A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications
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Issue 5
1.Introduction to the Special Issue on the 2009 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
2.24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13 $mu$ m SiGe BiCMOS Technology
3.Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2 2 802.11n MIMO WLAN SoC
4.A 300–800 MHz Tunable Filter and Linearized LNA Applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver
5.The Experimental Demonstration of a SASP-Based Full Software Radio Receiver
6.An Active Feedback Interference Cancellation Technique for Blocker Filtering in RF Receiver Front-Ends
7.Effect of Substrate Contact Shape and Placement on RF Characteristics of 45 nm Low Power CMOS Devices
8.A 10-bit Charge-Redistribution ADC Consuming 1.9 $mu$W at 1 MS/s
9.A Low-Power Capacitive Charge Pump Based Pipelined ADC
10.An Amorphous-Silicon Operational Amplifier and Its Application to a 4-Bit Digital-to-Analog Converter
11.A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop
12.A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS
13.A Low THD, Low Power, High Output-Swing Time-Mode-Based Tunable Oscillator Via Digital Harmonic-Cancellation Technique
14.Multi-Level Amplitude Modulation of a 16.8-GHz Class-E Power Amplifier With Negative Resistance Enhanced Power Gain for 400-Mbps Data Transmission
15.Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs
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Issue 6
1.A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS
2.A High-Resolution Low-Power Incremental ΔΣ ADC With Extended Range for Biosensor Arrays
3.A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
4.A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth
5.A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops
6.An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback
7.A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS
8.A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber
9.An Energy-Efficient Equalized Transceiver for RC-Dominant Channels
10.Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS
11.A Low-Voltage Energy-Sampling IR-UWB Digital Baseband Employing Quadratic Correlation
12.Energy-Efficient Design Methodologies：High-Performance VLSI Adders
13.A Differential Data-Aware Power-Supplied (D AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications
14.A Sub-uW Embedded CMOS Temperature Sensor for RFID Food Monitoring Application
15.Correction to “A 1 MHz Bandwidth, 6 GHz 0.18um CMOS Type-I ΔΣ Fractional-N Synthesizer for WiMAX Applications” [Dec 09 3244-3252]
16.Patent Abstracts
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Issue 7
1.Introduction to the Special Issue on the 35th European Solid-State Circuits Conference (ESSCIRC 2009)
2.Energy Supply and ULP Detection Circuits for an RFID Localization System in 130 nm CMOS
3.A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI
4.A 0.06 mm$^{2}$ 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS
5.A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS
6.A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications
7.An 11.1 Gbps Analog PRML Receiver for Electronic Dispersion Compensation of Fiber Optic Communications
8.A 16$, times $16 Pixel Distance Sensor With In-Pixel Circuitry That Tolerates 150 klx of Ambient Light
9.A 134-Pixel CMOS Sensor for Combined Time-of-Flight and Optical Triangulation 3-D Imaging
10.Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique
11.A 3-V, 6-Bit C-2C Digital-to-Analog Converter Using Complementary Organic Thin-Film Transistors on Glass
12.Closed-Loop Class-D Amplifier With Nonlinear Loop Integrators
13.A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition
14.A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving
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Issue 8
1.Introduction to the Special Issue on the IEEE 2009 Custom Integrated Circuits Conference
2.A 120 dB Dynamic Range 400 mW Class-D Speaker Driver With Fourth-Order PWM Modulator
3.Auto Correction Feedback for Ripple Suppression in a Chopper Amplifier
4.Area- and Power-Efficient Monolithic Buck Converters With Pseudo-Type III Compensation
5.Continuous-Time Input Pipeline ADCs
6.A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing
7.A 3.1 mW Continuous-Time ΔΣ Modulator With 5-Bit Successive Approximation Quantizer for WCDMA
8.An Embedded All-Digital Circuit to Measure PLL Response
9.Two-Dimensions Vernier Time-to-Digital Converter
10.A 2.4-GHz Low-Power All-Digital Phase-Locked Loop
11.A 3*3.8 Gb/s Four-Wire High Speed I/O Link Based on CDMA-Like Crosstalk Cancellation
12.A 5 Gbps 0.13 um CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links
13.Cognitive Radio Design Challenges and Techniques
14.Progress and Challenges Towards Terahertz CMOS Integrated Circuits
15.Injection-Locked CMOS Frequency Doublers for u-Wave and mm-Wave Applications
16.Triple-Push Operation for Combined Oscillation/Divison Functionality in Millimeter-Wave Frequency Synthesizers
17.An Active Transmitter Leakage Suppression Technique for CMOS SAW-Less CDMA Receivers
18.Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier
19.A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing
20.A mm-Wave Power-Harvesting RFID Tag in 90 nm CMOS
21.Correction to “An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and 98 dB THD” [Aug 09 2202-2211]
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Issue 9
1.Introduction to the Special Section on the 23rd Bipolar/BiCMOS Circuits and Technology Meeting
2.A Subharmonic Receiver in SiGe Technology for 122$~$GHz Sensor Applications
3.An Integrated 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and 20–28 GHz Frequency Synthesizer for Software-Defined Radio Applications
4.An X-Band Transformer-Coupled Varactor-Less Quadrature Current-Controlled Oscillator in 0.18 SiGe BiCMOS Technology
5.A 0.13 um SiGe BiCMOS Technology Featuring fT/fmax of 240/330 GHz and Gate Delays Below 3 ps
6.Parametric Mismatch Characterization for Mixed-Signal Technologies
7.A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems
8.Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications
9.A 60-GHz OOK Receiver With an On-Chip Antenna in 90 nm CMOS
10.Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio
11.Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-um Standard CMOS
12.An Ultralow-Power Receiver for Wireless Sensor Networks
13.Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping
14.A Floating-Gate-Based Field-Programmable Analog Array
15.A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback
16.Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector
17.A Low-Phase-Noise Multi-Phase Oscillator Based on Left-Handed LC-Ring
18.Distributed Parametric Resonator：A Passive CMOS Frequency Divider
19.A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS
20.A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins—Write/Read Assist Techniques for 1-V Operated Memory Cells
21.A 9-bit, 14 μW and 0.06 mm $^{2}$ Pulse Position Modulation ADC in 90 nm Digital CMOS
22.A High-Speed Current-Mode Data Driver With Push-Pull Transient Current Feedforward for Full-HD AMOLED Displays
23.A 6- uW Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology
24.An Efficiency-Enhanced Auto-Reconfigurable 2*/3* SC Charge Pump for Transcutaneous Power Transmission
25.An Integrated ISFETs Instrumentation System in Standard CMOS Technology
26.A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC
27.An Integrated 256-Channel Epiretinal Prosthesis
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Issue 10
1.Introduction to the 31st Annual IEEE Compound Semiconductor Integrated Circuit Symposium
2.A 120–145 GHz Heterodyne Receiver Chipset Utilizing the 140 GHz Atmospheric Window for Passive Millimeter-Wave Imaging Applications
3.An 18-Gb/s, Direct QPSK Modulation SiGe BiCMOS Transceiver for Last Mile Links in the 70–80 GHz Band
4.A Passive W-Band Imaging Receiver in 65-nm Bulk CMOS
5.A 0.25 um InP DHBT 200 GHz+ Static Frequency Divider
6.A Low-Loss 50–70 GHz SPDT Switch in 90 nm CMOS
7.MMIC LNAs for Radioastronomy Applications Using Advanced Industrial 70 nm Metamorphic Technology
8.A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS
9.High Efficiency WCDMA Power Amplifier With Pulsed Load Modulation (PLM)
10.A Highly Linear Two-Stage Amplifier Integrated Circuit Using InGaP/GaAs HBT
11.A 140 dB-CMRR Current-Feedback Instrumentation Amplifier Employing Ping-Pong Auto-Zeroing and Chopping
12.An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing
13.A Delta-Sigma Pulse-Width Digitization Technique for Super-Regenerative Receivers
14.A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS
15.A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors
16.A Low Phase-Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers
17.A 86 MHz–12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS
18.Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise
19.Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements
20.Ferroelectric(Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives
21.Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories
22.A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations
23.A Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers
24.A 9 uA, Addressable Gen2 Sensor Tag for Biosignal Acquisition
25.Comments and Corrections
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Issue 11
1.Introduction to the Special Section on the 2009 Asian Solid-State Circuits Conference (A-SSCC'09)
2.A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
3.A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
4.An Integrated Linear Regulator With Fast Output Voltage Transition for Dual-Supply SRAMs in DVFS Systems
5.An IF Bandpass Filter Based on a Low Distortion Transconductor
6.A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling
7.A 25-GHz Compact Low-Power Phased-Array Receiver With Continuous Beam Steering in CMOS Technology
8.A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer
9.A 700-uW Wireless Sensor Node SoC for Continuous Real-Time Health Monitoring
10.A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller
11.A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS
12.Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis
13.A 26.9 K 314.5 Mb/s Soft (32400,32208) BCH Decoder Chip for DVB-S2 System
14.A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers
15.0.5-V Low-VT CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays
16.A 0.5-uVrms 12-uW Wirelessly Powered Patch-Type Healthcare Sensor for Wearable Body Sensor Network
17.A Low-Energy Inductive Coupling Transceiver With Cm-Range 50-Mbps Data Communication in Mobile Device Applications
18.A 0.5 mm$^{2}$ Power-Scalable 0.5–3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler
19.A Low SIR Impulse-UWB Transceiver Utilizing Chirp FSK in 0.18 um CMOS
20.A System-on-Chip EPC Gen-2 Passive UHF RFID Tag With Embedded Temperature Sensor
21.A 2*25-Gb/s Receiver With 2：5 DMUX for 100-Gb/s Ethernet
22.Phase Error Calibration Technique for Rotary Traveling Wave Oscillators
23.50–250 MHz ΔΣ DLL for Clock Synchronization
24.The Speed–Power Trade-Off in the Design of CMOS True-Single-Phase-Clock Dividers
25.A Low-Power Fast-Transient 90-nm Low-Dropout Regulator With Multiple Small-Gain Stages
26.Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
Issue 11.part01.rar
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Issue 11.part02.rar
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Issue 11.part03.rar
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Issue 11.part04.rar
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Issue 11.part05.rar
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Issue 11.part06.rar
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Issue 11.part07.rar
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Issue 11.part08.rar
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Issue 11.part09.rar
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Issue 11.part10.rar
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发表于 2010-10-31 11:53:41
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