HV ESD protection-2

jian1712 · 发表于 2010-5-26 18:20:12

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

本帖最后由 jian1712 于 2010-5-26 18:33 编辑

Lateral DMOS design for ESD robustness

abstract
This paper presents the design of efficient ESD protection in lateral DMOS (LDMOS) power transistor. Using characterization of the LDMOS transistor under ESD conditions with various gate and drain clamps, the design for minimum power dissipation is established. The results show that for ESD regime of pulses the channel heating effects are minimum and that optimum ESD level can be achieved by driving the device into maximum possible MOS conduction. Based on these results, an empirical formula for effective ESD design is derived.

Lateral DMOS design for ESD robustness.pdf (361.25 KB, 下载次数: 202 )

ESD protection solutions for high voltage technologies
http://www.eetop.cn/bbs/thread-254145-1-1.html
Other esd papers
http://www.eetop.cn/bbs/thread-254229-1-1.html

Layout Dependence of ESD Characteristics on High Voltage LDMOS Transistors

Layout Dependence of ESD Characteristics on High Voltage LDMOS Transistors.rar (1.72 MB, 下载次数: 243 )