HV ESD protection-2

jian1712 · 发表于 2010-5-26 18:20:12

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本帖最后由 jian1712 于 2010-5-26 18:33 编辑

Lateral DMOS design for ESD robustness

abstract
This paper presents the design of efficient ESD protection in lateral DMOS (LDMOS) power transistor. Using characterization of the LDMOS transistor under ESD conditions with various gate and drain clamps, the design for minimum power dissipation is established. The results show that for ESD regime of pulses the channel heating effects are minimum and that optimum ESD level can be achieved by driving the device into maximum possible MOS conduction. Based on these results, an empirical formula for effective ESD design is derived.

Lateral DMOS design for ESD robustness.pdf (361.25 KB, 下载次数: 202 )

ESD protection solutions for high voltage technologies
http://www.eetop.cn/bbs/thread-254145-1-1.html
Other esd papers
http://www.eetop.cn/bbs/thread-254229-1-1.html

Layout Dependence of ESD Characteristics on High Voltage LDMOS Transistors

Layout Dependence of ESD Characteristics on High Voltage LDMOS Transistors.rar (1.72 MB, 下载次数: 243 )

jian1712 · 发表于 2010-5-27 17:35:44

顶一下，怎么没有人光顾阿

alexpanait · 发表于 2010-5-28 01:10:59

keep it up, thx.

jian1712 · 发表于 2010-6-2 12:52:16

顶一下，怎么没有人光顾阿

091120057 · 发表于 2010-6-2 19:19:42

kankanakanaknana

alenanderson · 发表于 2010-6-6 12:50:22

thanks for sharing

alenanderson · 发表于 2010-6-6 12:59:42

thanks. good book

Sweetlover · 发表于 2010-6-21 15:24:42

是papers吗？

chase_kinetic · 发表于 2010-6-21 15:59:36

thanks

chase_kinetic · 发表于 2010-6-21 16:02:40

great!

[资料] HV ESD protection-2

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