【免费】发几篇最近两年（2008年和2009年）RFIC transceiver的Thesis

christon

【免费】发几篇最近两年（2008年和2009年）RFIC transceiver的Thesis

[Thesis][2009]Architectures and integrated circuits for RF and mm-wave multiple-antenna systems on silicon
Abstract
This thesis presents unique architectures for the implementation of multiple-antenna sys-
tems at millimeter-wave frequencies on silicon-based processes.
Passive components play a key role in virtually every RF building block of a wire-
less transceiver. An overview of distributed passive components that are suitable for
millimeter-wave operation on silicon-based processes is provided in this thesis. A 0.18um
CMOS 26GHz complementary current-sharing oscillator topology is presented that, in
conjunction with a high-quality coplanar-stripline-based resonator, achieves state-of-the-
art phase-noise performance. The use of transformers to build high-quality integrated
resonators is investigated. It is found that, contrary to prior claims, integrated trans-
formers achieve no improvement over single spiral inductors in resonator quality factor
(Q) when subject to area and elective-inductance constraints. A theoretical formulation
for the impact of passive loss on the noise performance of low-noise amplifers (LNAs)
is also developed. A 0.13um SiGe E-band low-noise amplifer is implemented to support
the formulation.
A Variable-Phase Ring Oscillator and Phase-Locked Loop (VPRO-PLL) architec-
ture for integrated phased arrays is presented. The nonlinear multi-functional circuit
xxiieliminates key phased-array-transceiver building blocks, such as mixers, power split-
ters/combiners and phase shifters, by harnessing the injection-locking properties of a
tuned ring oscillator locked in a PLL. A detailed theoretical analysis of performance
metrics, such as sensitivity, linearity and array performance in the presence of process
mismatches, is given. Experimental results from two highly-integrated phased-array pro-
totypes, implemented in 0.13um CMOS and operating in the vicinity of 24GHz, are pro-
vided. The prototypes achieve similar functionality to prior works at the same frequency,
but consume a fraction of the area and power.
An RF-Multibeam Spatio-Temporal RAKE (ST-RAKE) transceiver architecture for
radar is proposed. The architecture exploits orthogonal codes in conjunction with an RF-
multibeam matrix to isolate not only line-of-sight reflections but multipath reflections as
well to glean more information about the scene being imaged. A highly-integrated, 4-
channel, 90nm CMOS, 24-26GHz prototype that targets vehicular-radar applications is
implemented to validate the principle of the architecture. The prototype is expected to
serve as a testbed for future studies pertaining to code and waveform design for such
MIMO radars.

christon

[Thesis][2009]Advanced Architectures for Next Generation Wireless Integrated Circuits
Abstract
In this thesis, we present and discuss two advanced architectures of wireless inte-
grated circuits.
In the first part of this thesis we will focus on the design of a inductorless re-
ceiver, which include a LNA, mixer and frequency synthesizer. Inductors are used
in RF design to extend the bandwidth by resonating out the load and/or parasitic
capacitance. However, on-chip inductors are large and cannot be ported easily from
one process to the next. Due to modern CMOS scaling, inductorless RF design is
rapidly becoming possible. In this thesis we describe a new methodology for designing
the RF frontends necessary for the wideband 1GHz-10GHz bandwidth in a 0.13um
CMOS technology. To validate our design methodology two receiver RF frontends
were designed; a traditional inductor based design and an inductorless design. A
common-gate LNA transconductor is followed by a capacitive peaking LNA-mixer
pair (CPLM). Measurement results indicate that CPLM with the same bandwidth
has better linearity, comparable noise figure and uses only 17% more power. The
silicon area for the CPLM is only 22% of the IPLM. Both designs can be mated with
an inductorless, ring-oscillator based, wide lock range and low power PLL also shown
in this thesis.
We present theory and prototype results for injection-locked frequency dividers
based on differential ring oscillators (D-ILFD) and single-ended ring oscillators (S-
ILFD), which can be locked to all harmonics (i.e., even and odd). We have developed
a general theory for lock range and phase noise for all harmonics for both topologies.
Measurement results for the D-ILFD and the S-ILFD show that the lock range de-
creases with increasing harmonics at the low harmonics while leveling on for larger
division ratios. Measured integrated phase noise for D-ILFD and S-ILFD also show
that the integrated phase noise decreases with increasing harmonics. The measure-
iiment results corroborate our theory. Ring oscillator based D-ILFDs and S-ILFDs are
compact and consume low power making them well suited for wideband low power
PLLs.
We exploit the ring VCO based on an updated Maneatis delay cell with self-
boosted biased techniques, which has a ultra wide tuning range of 1 GHz to 10.3GHz.
The injection-locked frequency divider (ILFD), which can lock to all harmonics, has
been used. A wide lock range, low power PLL based ring VCO and ILFD has been
designed for UWB radio. Experimental results indicate that integrated phase noise
is below a 30
and power consumption is only 8.1 mA to 21.85 mA for the entire
frequency bands.
In the second part of this thesis, we focus on noise isolation for mixed-signal
(RF/analog/digital) design in CMOS 3D ICs. Faraday cages have traditionally been
used to provide isolation from electromagnetic fields. In this thesis, we describe the
use of Faraday cages for reducing crosstalk in 3D ICs. We validate our methodol-
ogy with a combination of simulation and measurements from fabricated prototype
designs. Measurement and simulation results show that the crosstalk between the
transmitter and receiver reduces by about 75dB up to 10GHz by using a Faraday
cage in combination with tier-to-tier isolation, which is one of best performance re-
ported so far. Measurement results indicate that the Faraday cages have no effect
on the S-parameters and linearity of inductorless RF circuits. We further develop a
lumped equivalent model for crosstalk with and without a Faraday cage. There is
good agreement between measurement, 3D electromagnetic simulation and lumped
circuit simulation.

lgy747

thanks

christon

[Thesis][2008]Low-Voltage and Low-Power Silicon Transceivers and Receivers for W-Band and D-Band Applications
Abstract
This thesis presents the design and implementation of low-voltage low-power transceivers and receivers in SiGe HBT and CMOS technologies which operate above
75 GHz...

christon

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christon

[Thesis][2008]CMOS MILLIMETER AND SUBMILLIMETER-WAVE COMPONENTS
With continued introduction of new wireless applications, the available spectrum is
becoming crowded. Because of this, interests for developing circuits and systems operating at
higher frequencies have been increasing larger bandwidth and propagation properties of signals
in the frequency range from 100 GHz to 3 THz have led to the recent increase in research efforts.  
For the communication over 30m, use of antennas are better than using transmission lines
at the frequency above 60 GHz. Use of on-chip antennas at high frequencies makes systems
compact and lower cost, as well as potentially improve their performance. The impact of realistic
metal interference structures which can significantly modify the characteristics of on-chip
antennas, such as a power grid, local clock trees and data lines have been investigated using EM
simulations. In the presence of a power grid, the antenna pair |S12| can be traded off for improved
stability of antennas characteristics and the predictability of on-chip antenna characteristics.  
The radiation of a patch antenna is due to the fringing fields. The ground plane in the patch
antenna decreases the coupling to near by circuits. The  design of patch antenna in CMOS
processes is limited by the fixed relatively low dielectric thicknesses. These limit the input
resistance and efficiency. The bond wires change the radiation direction by ~13o at the distance
12  
of 50 μm from a patch for 250 GHz operation and decrease the input resistance by about 4 Ω.
Increasing the separation to 150 μm, make the impact of bond wires negligible.  
A 182-GHz Schottky diode detector is demonstrated in  foundry 130-nm CMOS
technology. A 182-GHz AM modulator is implemented by changing the gate bias of PMOS
current source of a push-push oscillator which utilizes the 2nd
order harmonics. The operation is
verified by the observation of 91-GHz AM signals at the fundamental using an OML harmonic
mixer. The noise performance of a 250 GHz Schottky barrier diode detector with an on-chip
patch antenna in 90 nm CMOS also have analyzed.  
To overcome the difficulties of electrical measurement techniques for submillimeter-wave
circuits, optical techniques  are utilized. The power and spectrum of 250-GHz and 410-GHz
push-push oscillators have been measured using a bolometer (HD-3, IR Lab) and FTIR (IFS
113v, Bruker). A 250-GHz push–push oscillator with an on-chip patch antenna fabricated using a
90-nm CMOS process is demonstrated. A ring oscillator is incorporated for the generation of
250-GHz AM signals. The 125-GHz AM signal is measured using a harmonic mixer and a
spectrum analyzer. The radiated second harmonic power from the patch antenna is about -32
dBm. A 410-GHz push–push oscillator with an on-chip patch antenna fabricated using low
leakage transistors of a 45-nm CMOS process with 6 metal layers is demonstrated. The patch
antenna size is 200 x 200 μm2
. The radiated second harmonic power from the patch antenna is
about -49 dBm. The 410-GHz operating frequency is the highest  among the transistor circuits
fabricated in any technology including the III-V  technologies. These suggest the possibility of
CMOS THz systems.

christon

[Thesis][2008][UCLA]CMOS Circuits and Devices Beyond 100 GHz

christon

[Thesis][2008][UCLA]A New Transceiver Architecture for the 60-GHz Band

christon

[Thesis][2008][UCB]Millimeter - Wave CMOS Power Amplifiers Design
Abstract
In the last few years we have seen an increased interest in millimeter-wave CMOS
circuits and communication systems both in academia and industry. The feasibility of
CMOS circuits at 60 GHz, the rising interest in digital video, short range, and other high
data rate applications, along with the worldwide availability of unlicensed spectrum
around 60 GHz have spurred a wave of research targeting integrated 60 GHz CMOS
transceivers as a way to achieving low cost, highly integrated, high bandwidth, high data
rate communication systems.
In recent years, a number of 60 GHz CMOS building blocks and integrated
receivers have been demonstrated. However, the low supply voltage, thin gate oxide, low
breakdown voltage, lossy silicon substrate, and power gain - output power tradeoff of
CMOS technology result in the millimeter wave power amplifier being the most difficult
block to implement in CMOS. A number of 60 GHz CMOS power amplifiers employing
different topologies have been reported to date, however the output power has been
relatively low, limiting the amplifiers to short-range applications. It is becoming 2
increasingly important to use more efficient power combining techniques in order to
increase the output power capability of power amplifiers in order to enable medium and
long-range applications.
This research aims at exploring the challenges facing the design and
implementation of 60 GHz power amplifiers in standard 90 nm CMOS processes. The
design, modeling, and layout optimization of both passive structures such as transmission
lines, capacitors, RF pads as well as active devices operating at 60 GHz are investigated.
A low-loss power combining technique taking advantage of millimeter-wave amplifiers
topologies is presented. Four power amplifiers are implemented in a standard 90 nm IV
CMOS process. Record performance is reached in terms of ldB compression and
saturation output power.

christon

[Thesis][2008][UCB]A Baseband Mixed-Signal Receiver Front-End for 1Gbps Wireless Communications at 60GHz