Design of CMOS ring oscillator

analogworld

Design of CMOS ring oscillator
PEN FINNSTAM & MIKAEL SODERLUND
Circuit Design Group
Department of singals and systems
Chalmers university of technology
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nesta

Abstract
In this thesis we evaluate the ring oscillator implemented in CMOS. This evaluation is done by exploring the ring oscillator both in theory and practice. We have designed a VCO containing a 7-stage differential ring oscillator. It has been designed from hand calculation and verified by simulations on both schematic and layout level in a 0.5-μm process. The target performance of the VCO is a centre frequency of 200 MHz and a phase-noise requirement of –100 dBc @100 kHz. The designed ring oscillator, without the bias replica circuit meets the target performance. However, the complete VCO does not meet the target performance due to the poor noise performance of the bias replica circuit. The implemented VCO was compared with an existing LC oscillator with almost the same centre frequency and phase-noise requirements. The result shows that the major trade off between the ring oscillator and LC oscillator is in area and power consumption. That is, the ring oscillator consumes more power but requires less area. Since finer process geometries allows smaller device area to be used, the designed VCO was scaled into a 0.25-μm process. This redesign showed no great benefits with finer processes since minimum channel length generates significantly more noise of the MOSFET device.

criffs

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scpuke

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s8553warrior

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asdfjkl

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jackal0716

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joe_chen

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