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A 10-bit, 100 MS/s Analog-to-Digital Converter in 1-µm CMOS
ABSTRACT OF THE DISSERTATION
A 10-bit 100 Msample-per-Second
Analog-to-Digital Converter
in 1-mm CMOS
by
Kwang Young Kim
Doctor of Philosophy in Electrical Engineering
University of California, Los Angeles, 1996
Professor Asad A. Abidi, Chair
Applications such as high-end video signal processing, high performance
digital communications, and medical imaging require ADCs with sample rates
approaching 100 MS/s and a dynamic range at the Nyquist bandwidth close to 60
dB. In response to these needs, there is a continued search for architectures and
circuit techniques enabling a monolithic ADC to meet these specifications with a
reasonable chip area and power dissipation. It is of particular interest that if such an
ADC is fabricated in a standard CMOS technology.
This work addresses some of the known problems inherent in timeinterleaved,
or parallel, pipeline ADCs with a new architecture. A prototype of this
architecture demonstrates, for the first time, 10-bit operation at the maximum
sampling rate up to 95 MHz in 1 mm CMOS technology. It attains 59.5 dB SNDR
at a low conversion rate, and more than 50 dB SNDR at 50MHz input frequency
with a 95 MHz conversion rate. By using a minor offset control to suppress the fs/2
tone, 65 dB spurious free dynamic range (SFDR) is achieved. The simulated bit
error rate is less than 10-10. The ADC implemented in fully differential circuitry
uses the 2-channel 3-stage pipeline architecture. Each stage converts 4-bits, and
2-bits from 12-bit are used for digital error correction. Because all the digital clock
signals are generated from the on-chip clock buffer, it requires a single full speed
clock signal. The active chip area is 50 mm2 and the ADC dissipates 1.2 W from a
single 5 V power supply. |
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