|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
Springer 2007年Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies
About this book
In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.
Written for:
System and circuit level design engineers in research and development, graduate and post-graduate students, courses on advanced digital CMOS design
Keywords:
[ 本帖最后由 eexuke 于 2008-11-5 14:20 编辑 ] |
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2008-11-5 14:13:27
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!