Switched-Current Circuits---Mixed Analog-Digital Systems

kevinwjs

1. Introduction ............................................................................................................. 1
1.1 SWITCHED-CURRENT TECHNIQUES.................................. 2
1.2 ABOUT THIS THESIS ....................................................... 3
1.3 REFERENCES................................................................. 5
Part I: An Introduction to the SI Technique............................................................ 7
2. SI Circuits................................................................................................................ 9
2.1 CURRENT-MODE BUILDING BLOCKS................................. 9
2.1.1 The current mirror .................................................. 9
2.1.2 First and second generation SI memory cells.................... 10
2.1.3 OTA based current S/H circuits ................................... 11
2.1.4 Comparators......................................................... 12
2.1.5 D/A-converters ...................................................... 12
2.2 NON-IDEAL EFFECTS ...................................................... 13
2.2.1 MOS transistor mismatch .......................................... 13
2.2.2 Conductance ratio errors ........................................... 16
2.2.3 Clock-feedthrough.................................................. 17
2.2.4 Noise ................................................................. 21
2.2.5 Settling ............................................................... 25
2.2.6 Voltage drop......................................................... 26
2.2.7 Jitter .................................................................. 26
2.2.8 Summary of non-ideal effects ..................................... 27
2.3 CLOCK-FEEDTHROUGH COMPENSATION........................... 27
2.3.1 Attenuation techniques ............................................. 27
2.3.2 Cancellation techniques ............................................ 28
2.3.3 Algorithmic techniques............................................. 30
2.3.4 Fully-differential, feedforward and feedback techniques . . . . . . 31
2.3.5 Adaptive techniques ................................................ 31
2.3.6 Zero-voltage switching techniques................................ 32
2.3.7 CFT compensation techniques used in this work ............... 32
2.4 CURRENT SAMPLE-AND-HOLD EVOLUTION........................ 33
2.5 REFERENCES................................................................. 35
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3. SI Systems ............................................................................................................. 43
3.1 SAMPLED-DATA FILTERS................................................. 43
3.1.1 FIR-filters............................................................ 43
3.1.2 IIR-filters ............................................................ 44
3.1.3 Miscellaneous filters................................................ 46
3.1.4 Design methodology and analysis ................................ 47
3.1.5 Influence of SI circuit imperfections on sampled-data
filters......................................................................... 47
3.2 A/D CONVERTERS........................................................... 47
3.2.1 Nyquist A/D Converters ........................................... 48
3.2.2 Oversampling D-å A/D converters ............................... 52
3.2.3 Influence of SI circuit imperfections on ADCs.................. 53
3.3 DESIGN AUTOMATION FOR SI SYSTEMS ............................ 53
3.3.1 CAD tool structure for automatic layout generation............. 54
3.3.2 Layout style.......................................................... 55
3.4 REFERENCES................................................................. 56
Part II: Novel SI Circuit Realizations................................................................... 65
4. Current-Mode N-Port Adaptors For Wave SI Filters........................................ 67
4.1 ABSTRACT .................................................................... 67
4.2 INTRODUCTION ............................................................. 67
4.3 THE USE OF WAVE FILTERS ............................................. 67
4.4 PROPOSED REALIZATION OF N-PORT ADAPTORS................. 68
4.5 FILTER REALIZATION EXAMPLE ....................................... 69
4.6 SIMULATION RESULTS.................................................... 71
4.7 CONCLUSIONS............................................................... 71
4.8 ACKNOWLEDGMENTS..................................................... 71
4.9 REFERENCES................................................................. 71
5. New Clock-Feedthrough Compensation Scheme For Switched-
Current Circuits ....................................................................................................... 73
5.1 ABSTRACT .................................................................... 73
5.2 INTRODUCTION ............................................................. 73
5.3 CLOCK-FEEDTHROUGH IN SI CIRCUITS............................. 73
5.4 RELATION BETWEEN THE CFT AND THE MIRROR GAIN. . . . . . . . 74
5.5 PROPOSED CFT REDUCTION SCHEME................................ 75
5.6 SIMULATION AND RESULTS............................................. 76
5.7 CONCLUSIONS............................................................... 76
5.8 ACKNOWLEDGMENTS..................................................... 77
5.9 REFERENCES................................................................. 77
Part III: Contributions to SI Circuit Design and Theory .................................... 79
6. Clock-Feedthrough Compensated First-Generation SI Circuits and
Systems......................................................................................................................81
6.1 ABSTRACT .................................................................... 81
6.2 INTRODUCTION ............................................................. 81
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6.3 CLOCK-FEEDTHROUGH COMPENSATION IN SI CIRCUITS. . . . . 82
6.3.1 Clock-feedthrough modeling ...................................... 82
6.3.2 Large-signal CFT error current.................................... 83
6.3.3 Complete CFT cancellation ........................................ 84
6.3.4 Coefficient matching sensitivity................................... 85
6.4 MEMORY CELL DESIGN OPTIONS...................................... 86
6.4.1 Optimizing an arbitrary goal function............................. 87
6.4.2 Minimizing CFT .................................................... 88
6.5 SWITCHED-CURRENT DELTA-SIGMA MODULATOR.............. 88
6.6 EXPERIMENTAL RESULTS ............................................... 90
6.7 CONCLUSIONS............................................................... 92
6.8 ACKNOWLEDGMENTS..................................................... 92
6.9 REFERENCES................................................................. 92
7. Distortion in sampling ......................................................................................... 95
7.1 ABSTRACT .................................................................... 95
7.2 INTRODUCTION ............................................................. 95
7.3 SAMPLING OF ANALOG SIGNALS ..................................... 95
7.4 THE DISADVANTAGE OF USING CMOS SWITCHES IN
HIGH-SPEED SAMPLING....................................................... 98
7.5 COMPARISON OF SAMPLING TECHNIQUES ........................ 99
7.6 MATCHING SENSITIVITY................................................. 101
7.7 CONCLUSIONS............................................................... 102
7.8 REFERENCES................................................................. 103
8. Sampling jitter in high-speed SI circuits ........................................................ 105
8.1 ABSTRACT .................................................................... 105
8.2 INTRODUCTION ............................................................. 105
8.3 SAMPLING TIME UNCERTAINTY....................................... 105
8.4 REDUCING SAMPLING TIME UNCERTAINTY....................... 107
8.4.1 Random jitter ........................................................ 107
8.4.2 Signal dependent jitter.............................................. 108
8.5 CONCLUSIONS............................................................... 110
8.6 ACKNOWLEDGMENTS..................................................... 110
8.7 REFERENCES................................................................. 111
9. Design of power supply lines in high-performance SI and currentmode
circuits............................................................................................................ 113
9.1 ABSTRACT .................................................................... 113
9.2 INTRODUCTION ............................................................. 113
9.3 VOLTAGE DROP ON POWER SUPPLY WIRES........................ 114
9.4 DESIGN CONSIDERATIONS .............................................. 115
9.4.1 Quiescent point shift................................................ 115
9.4.2 Offset and distortion................................................ 116
9.5 CONCLUSIONS............................................................... 117
9.6 ACKNOWLEDGMENTS..................................................... 118
9.7 REFERENCES................................................................. 118
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Part IV: SI Circuit Implementations.................................................................... 119
10. A Low Voltage Wave SI Filter Implementation using Improved
Delay Elements ....................................................................................................... 121
10.1 ABSTRACT................................................................... 121
10.2 INTRODUCTION............................................................ 121
10.3 WAVE SI FILTERS.......................................................... 122
10.3.1 Background ........................................................ 122
10.3.2 Current-mode circuit realization of N-port adaptors........... 122
10.4 SI MEMORY CELLS ........................................................ 123
10.4.1 Clock feedthrough in SI delay elements ........................ 123
10.4.2 Cancellation of clock feedthrough............................... 124
10.5 POTENTIAL FOR AUTOMATIC GENERATION...................... 125
10.6 PERFORMANCE ............................................................ 126
10.7 CONCLUDING REMARKS ............................................... 127
10.8 REFERENCES ............................................................... 127
11. A 3.3 V 11 Bit Delta-Sigma Modulator Using First-Generation SI
Circuits.....................................................................................................................129
11.1 ABSTRACT................................................................... 129
11.2 INTRODUCTION............................................................ 129
11.3 MODULATOR STRUCTURE.............................................. 129
11.4 IMPLEMENTATION AND MEASUREMENT .......................... 131
11.5 CONCLUSIONS ............................................................. 132
11.6 ACKNOWLEDGMENTS ................................................... 132
11.7 REFERENCES ............................................................... 132
12. A 3 V, 10 bit, 6.4 MHz Switched-Current CMOS A/D Converter
Design.......................................................................................................................135
12.1 ABSTRACT................................................................... 135
12.2 INTRODUCTION............................................................ 135
12.3 A/D CONVERTER ARCHITECTURE.................................... 136
12.4 CIRCUIT REALIZATION .................................................. 137
12.5 SIMULATION RESULTS .................................................. 138
12.6 CONCLUSIONS ............................................................. 141
12.7 ACKNOWLEDGMENTS ................................................... 141
12.8 REFERENCES ............................................................... 141
13. A Low-Voltage, 10-b Switched-Current ADC with 20 MHz Input
Bandwidth ................................................................................................................ 143
13.1 ABSTRACT................................................................... 143
13.2 INTRODUCTION............................................................ 143
13.3 A/D CONVERTER ARCHITECTURE.................................... 143
13.4 CIRCUIT IMPLEMENTATION ........................................... 145
13.5 EXPERIMENTAL RESULTS.............................................. 145
13.6 ACKNOWLEDGMENTS ................................................... 146
13.7 REFERENCES ............................................................... 146
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14. A 3V Switched-Current Pipelined Analog-to-Digital Converter in a
5V CMOS process................................................................................................... 149
14.1 ABSTRACT................................................................... 149
14.2 INTRODUCTION............................................................ 149
14.3 A/D CONVERTER ARCHITECTURE.................................... 150
14.4 CIRCUIT IMPLEMENTATION ........................................... 151
14.5 EXPERIMENTAL RESULTS.............................................. 152
14.6 CONCLUSIONS ............................................................. 155
14.7 ACKNOWLEDGMENTS ................................................... 155
14.8 REFERENCES ............................................................... 155
15. A 3V Wideband CMOS Switched-Current A/D-Converter Suitable
for Time-Interleaved Operation............................................................................ 157
15.1 ABSTRACT................................................................... 157
15.2 INTRODUCTION............................................................ 157
15.3 SWITCHED-CURRENT A/D CONVERTERS .......................... 158
15.4 RSD A/D CONVERTER ARCHITECTURE ............................. 159
15.5 CIRCUIT IMPLEMENTATION ........................................... 160
15.6 SIMULATION RESULTS .................................................. 162
15.6.1 System level simulations ......................................... 162
15.6.2 Circuit level simulations .......................................... 163
15.7 EXPERIMENTAL RESULTS.............................................. 165
15.8 PERFORMANCE COMPARISON ........................................ 169
15.9 CONCLUSIONS ............................................................. 172
15.10 ACKNOWLEDGMENTS.................................................. 172
15.11 REFERENCES.............................................................. 173
16. A Low-Voltage 32MS/s Parallel Pipelined Switched-Current ADC........... 177
16.1 ABSTRACT................................................................... 177
16.2 INTRODUCTION............................................................ 177
16.3 A/D CONVERTER ARCHITECTURE.................................... 177
16.4 CIRCUIT IMPLEMENTATION ........................................... 178
16.5 EXPERIMENTAL RESULTS.............................................. 179
16.6 ACKNOWLEDGMENTS ................................................... 181
16.7 REFERENCES ............................................................... 181
17. A Dual 3-V 32-MS/s CMOS Switched-Current ADC for
Telecommunication Applications ......................................................................... 183
17.1 ABSTRACT................................................................... 183
17.2 INTRODUCTION............................................................ 183
17.3 A/D CONVERTER ARCHITECTURE.................................... 184
17.4 CIRCUIT IMPLEMENTATION ........................................... 185
17.5 EXPERIMENTAL RESULTS.............................................. 186
17.5.1 ADC core cell ...................................................... 186
17.5.2 Parallel ADC ....................................................... 187
17.6 CONCLUSIONS ............................................................. 189
17.7 ACKNOWLEDGMENTS ................................................... 189
17.8 REFERENCES ............................................................... 189
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18. Conclusions ....................................................................................................... 191

soupdawn

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fireworker

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fireworker

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xiaoyingqun

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fanjx

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luoyih

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luoyih

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