有没有大佬用verilogA写过一个有时钟控制端的DAC

L_cj

在ahdlib库里找到了理想的8位DAC，想加个时钟端。

LSnowPine

输入信号加触发器也行

carl11223344

You can make output signal be triggered only if CLK is positive/negative edge, by utilizing @(cross(CLK-0.5*Vdd,+1))
all output expressions should be enclosed in begin end block, that followed by @(‧) analog event monitor.
Alternative way will be adding 8 control-switch (ideal relay) to your 8-bit digital DAC inputs