软核的DC综合

JOSHAU

大家dc综合的时候遇到有软核的都是用MC转换成硬核处理吗，我转换之后感觉和原本的比少了很多东西，MC感觉就是根据位宽写了一个。然后我读入转换后的硬核，以及编译出来的db文件，把原本的blk_mem_gen_v8.v删掉了，结果报了很多
Error:  C_USE_DEFAULT_DATA is not a parameter in module blk_mem_v8_4_10 (VER-216)
Error:  C_DEFAULT_DATA is not a parameter in module blk_mem_v8_4_10 (VER-216)问了ai让我再做一个模块封装他们两个，还有一些其他的处理，感觉好麻烦，不知道正常流程是不是也是这样的。这个是我的脚本：
redirect -tee -file run.log {
    # 库设置
    define_design_lib WORK -path "/home/ICer/NTT_project/sram/input/tcl/WORK"
    sh rm -rf [get_design_lib_path WORK]
    sh mkdir -p [get_design_lib_path WORK]

    # 缓存设置
    set_app_var cache_write ".cache"
    sh rm -rf [get_app_var cache_write]
    sh mkdir -p [get_app_var cache_write]
    set_app_var cache_read [get_app_var cache_write]
    set_app_var alib_library_analysis_path alib

    # 基础设置
    set_app_var hdlin_vrlg_std 2001
    set_app_var verilogout_no_tri true
    set_host_options -max_cores 6
    set_app_var suppress_errors [concat [get_app_var suppress_errors] "OPT-170" "VER-294"]

    # 路径和库设置
    set PRJ_DIR "/home/ICer/NTT_project/sram/input/rtl"
    set_app_var search_path [list /home/ICer/NTT_project/sram/input/rtl /home/ICer/NTT_project/sram/input]
    set_app_var target_library {
        /home/ICer/NTT_project/sram/input/scc018ug_hd_rvt_ss_v1p62_125c_basic.db
        /home/ICer/NTT_project/sram/input/blk_mem_v8_4_10_typical.db
        }
    set_app_var link_library [list * \
        /home/ICer/NTT_project/sram/input/scc018ug_hd_rvt_ss_v1p62_125c_basic.db \
        /home/ICer/NTT_project/sram/input/SP018RP_V1p0_max.db]

    set top_module top_module

    # 创建输出目录
    sh mkdir -p /home/ICer/NTT_project/sram/input/tcl/reports
    sh mkdir -p mapped

    # 读取设计文件
    set rtl_files {
        /home/ICer/NTT_project/sram/input/rtl/blk_mem_v8_4_10.v
        /home/ICer/NTT_project/sram/input/rtl/bram_16_control.v
        /home/ICer/NTT_project/sram/input/rtl/bram_16_control.v
/home/ICer/NTT_project/sram/input/rtl/bram_16_control_2.v
/home/ICer/NTT_project/sram/input/rtl/bram_ntt.v
/home/ICer/NTT_project/sram/input/rtl/bram_ntt_v.v
/home/ICer/NTT_project/sram/input/rtl/blk_w_4.v
/home/ICer/NTT_project/sram/input/rtl/blk_w_5.v
/home/ICer/NTT_project/sram/input/rtl/blk_w_6.v
/home/ICer/NTT_project/sram/input/rtl/blk_w_7.v
/home/ICer/NTT_project/sram/input/rtl/blk_64_0.v
/home/ICer/NTT_project/sram/input/rtl/blk_64_1.v
/home/ICer/NTT_project/sram/input/rtl/blk_32_0.v
/home/ICer/NTT_project/sram/input/rtl/blk_32_1.v
/home/ICer/NTT_project/sram/input/rtl/arrang_7.v
/home/ICer/NTT_project/sram/input/rtl/arrange_1.v
/home/ICer/NTT_project/sram/input/rtl/arrange_2.v
/home/ICer/NTT_project/sram/input/rtl/arrange_3.v
/home/ICer/NTT_project/sram/input/rtl/arrange_4.v
/home/ICer/NTT_project/sram/input/rtl/arrange_5.v
/home/ICer/NTT_project/sram/input/rtl/arrange_6.v
/home/ICer/NTT_project/sram/input/rtl/bf1.v
/home/ICer/NTT_project/sram/input/rtl/bf2.v
/home/ICer/NTT_project/sram/input/rtl/BF.v
/home/ICer/NTT_project/sram/input/rtl/bram32_control.v
/home/ICer/NTT_project/sram/input/rtl/bram64_control.v
/home/ICer/NTT_project/sram/input/rtl/bram64_control_2.v
/home/ICer/NTT_project/sram/input/rtl/bram_1.v
/home/ICer/NTT_project/sram/input/rtl/bram_2.v
/home/ICer/NTT_project/sram/input/rtl/bram_3.v
/home/ICer/NTT_project/sram/input/rtl/bram_4.v
/home/ICer/NTT_project/sram/input/rtl/bram_5.v
/home/ICer/NTT_project/sram/input/rtl/bram_6.v
/home/ICer/NTT_project/sram/input/rtl/bram_7.v
/home/ICer/NTT_project/sram/input/rtl/bram_32_control_2.v
/home/ICer/NTT_project/sram/input/rtl/buffer.v
/home/ICer/NTT_project/sram/input/rtl/buffer_2.v
/home/ICer/NTT_project/sram/input/rtl/buffer_4.v
/home/ICer/NTT_project/sram/input/rtl/buffer_8.v
/home/ICer/NTT_project/sram/input/rtl/buffer_16.v
/home/ICer/NTT_project/sram/input/rtl/control.v
/home/ICer/NTT_project/sram/input/rtl/Mont_reduce.v
/home/ICer/NTT_project/sram/input/rtl/mul.v
/home/ICer/NTT_project/sram/input/rtl/mul_1.v
/home/ICer/NTT_project/sram/input/rtl/mul_2.v
/home/ICer/NTT_project/sram/input/rtl/mul_2_2.v
/home/ICer/NTT_project/sram/input/rtl/mul_2_top.v
/home/ICer/NTT_project/sram/input/rtl/stage_1.v
/home/ICer/NTT_project/sram/input/rtl/stage_2.v
/home/ICer/NTT_project/sram/input/rtl/stage_3.v
/home/ICer/NTT_project/sram/input/rtl/stage_4.v
/home/ICer/NTT_project/sram/input/rtl/stage_5.v
/home/ICer/NTT_project/sram/input/rtl/stage_6.v
/home/ICer/NTT_project/sram/input/rtl/stage_7.v
/home/ICer/NTT_project/sram/input/rtl/stage_8.v
/home/ICer/NTT_project/sram/input/rtl/switch.v
/home/ICer/NTT_project/sram/input/rtl/top.v
/home/ICer/NTT_project/sram/input/rtl/top_module.v
    }
   
    foreach rtl_file $rtl_files {
        echo "Analyzing: $rtl_file"
        analyze -format verilog -library WORK $rtl_file
    }

    # Elaborate 并检查
    elaborate ${top_module}
    if {[get_designs -quiet $top_module] == ""} {
        echo "Error: Elaborate failed for $top_module"
        exit 1
    }
    current_design $top_module

    # 综合流程
    set_svf ${top_module}.svf
   
    set status [link]
    if {!$status} {
        echo "Error: link failed"
        exit 1
    }

    # 约束和综合
    source /home/ICer/NTT_project/sram/input/tcl/Top_256.sdc
    check_timing

    # 报告
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/check_design_pre.rpt {check_design -nosplit}
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/check_timing_pre.rpt {check_timing}
   
    # 编译
    compile_ultra -no_autoungroup -no_seq_output_inversion

    # 后处理
    remove_unconnected_ports [find -hier cell "*"]
    change_name -rules verilog -hier
    set_svf -off

    # 最终报告
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/check_design_post.rpt {check_design -nosplit}
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/check_timing_post.rpt {check_timing}
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/area.rpt {report_area -nosplit -hier}
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/violators.rpt {report_constraints -nosplit -all_violators -significant_digits 4}
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/timing.rpt {report_timing -nosplit -attributes -transition_time -max_path 5 -significant_digits 4}

    # 输出文件
    write -format verilog -hier -o mapped/${top_module}.v
    write -format ddc -hier -o mapped/${top_module}.ddc
    write_environment -format dctcl -environment_only -o mapped/${top_module}.tcl
    write_sdf mapped/${top_module}.sdf
    write_sdc -nosp mapped/${top_module}.sdc
}

ilmkduse

朋友，你发的是付费浏览，不花信元看不到

JOSHAU

   

ilmkduse 发表于 2025-10-24 13:19
朋友，你发的是付费浏览，不花信元看不到

抱歉，我以为这个是悬赏呢😭

JOSHAU

   

ilmkduse 发表于 2025-10-24 13:19
朋友，你发的是付费浏览，不花信元看不到

这个是脚本redirect -tee -file run.log {
    # 库设置
    define_design_lib WORK -path "/home/ICer/NTT_project/sram/input/tcl/WORK"
    sh rm -rf [get_design_lib_path WORK]
    sh mkdir -p [get_design_lib_path WORK]

    # 缓存设置
    set_app_var cache_write ".cache"
    sh rm -rf [get_app_var cache_write]
    sh mkdir -p [get_app_var cache_write]
    set_app_var cache_read [get_app_var cache_write]
    set_app_var alib_library_analysis_path alib

    # 基础设置
    set_app_var hdlin_vrlg_std 2001
    set_app_var verilogout_no_tri true
    set_host_options -max_cores 6
    set_app_var suppress_errors [concat [get_app_var suppress_errors] "OPT-170" "VER-294"]

    # 路径和库设置
    set PRJ_DIR "/home/ICer/NTT_project/sram/input/rtl"
    set_app_var search_path [list /home/ICer/NTT_project/sram/input/rtl /home/ICer/NTT_project/sram/input]
    set_app_var target_library {
        /home/ICer/NTT_project/sram/input/scc018ug_hd_rvt_ss_v1p62_125c_basic.db
        /home/ICer/NTT_project/sram/input/blk_mem_v8_4_10_typical.db
        }
    set_app_var link_library [list * \
        /home/ICer/NTT_project/sram/input/scc018ug_hd_rvt_ss_v1p62_125c_basic.db \
        /home/ICer/NTT_project/sram/input/SP018RP_V1p0_max.db]

    set top_module top_module

    # 创建输出目录
    sh mkdir -p /home/ICer/NTT_project/sram/input/tcl/reports
    sh mkdir -p mapped

    # 读取设计文件
    set rtl_files {
        /home/ICer/NTT_project/sram/input/rtl/blk_mem_v8_4_10.v
        /home/ICer/NTT_project/sram/input/rtl/bram_16_control.v
        /home/ICer/NTT_project/sram/input/rtl/bram_16_control.v
/home/ICer/NTT_project/sram/input/rtl/bram_16_control_2.v
/home/ICer/NTT_project/sram/input/rtl/bram_ntt.v
/home/ICer/NTT_project/sram/input/rtl/bram_ntt_v.v
/home/ICer/NTT_project/sram/input/rtl/blk_w_4.v
/home/ICer/NTT_project/sram/input/rtl/blk_w_5.v
/home/ICer/NTT_project/sram/input/rtl/blk_w_6.v
/home/ICer/NTT_project/sram/input/rtl/blk_w_7.v
/home/ICer/NTT_project/sram/input/rtl/blk_64_0.v
/home/ICer/NTT_project/sram/input/rtl/blk_64_1.v
/home/ICer/NTT_project/sram/input/rtl/blk_32_0.v
/home/ICer/NTT_project/sram/input/rtl/blk_32_1.v
/home/ICer/NTT_project/sram/input/rtl/arrang_7.v
/home/ICer/NTT_project/sram/input/rtl/arrange_1.v
/home/ICer/NTT_project/sram/input/rtl/arrange_2.v
/home/ICer/NTT_project/sram/input/rtl/arrange_3.v
/home/ICer/NTT_project/sram/input/rtl/arrange_4.v
/home/ICer/NTT_project/sram/input/rtl/arrange_5.v
/home/ICer/NTT_project/sram/input/rtl/arrange_6.v
/home/ICer/NTT_project/sram/input/rtl/bf1.v
/home/ICer/NTT_project/sram/input/rtl/bf2.v
/home/ICer/NTT_project/sram/input/rtl/BF.v
/home/ICer/NTT_project/sram/input/rtl/bram32_control.v
/home/ICer/NTT_project/sram/input/rtl/bram64_control.v
/home/ICer/NTT_project/sram/input/rtl/bram64_control_2.v
/home/ICer/NTT_project/sram/input/rtl/bram_1.v
/home/ICer/NTT_project/sram/input/rtl/bram_2.v
/home/ICer/NTT_project/sram/input/rtl/bram_3.v
/home/ICer/NTT_project/sram/input/rtl/bram_4.v
/home/ICer/NTT_project/sram/input/rtl/bram_5.v
/home/ICer/NTT_project/sram/input/rtl/bram_6.v
/home/ICer/NTT_project/sram/input/rtl/bram_7.v
/home/ICer/NTT_project/sram/input/rtl/bram_32_control_2.v
/home/ICer/NTT_project/sram/input/rtl/buffer.v
/home/ICer/NTT_project/sram/input/rtl/buffer_2.v
/home/ICer/NTT_project/sram/input/rtl/buffer_4.v
/home/ICer/NTT_project/sram/input/rtl/buffer_8.v
/home/ICer/NTT_project/sram/input/rtl/buffer_16.v
/home/ICer/NTT_project/sram/input/rtl/control.v
/home/ICer/NTT_project/sram/input/rtl/Mont_reduce.v
/home/ICer/NTT_project/sram/input/rtl/mul.v
/home/ICer/NTT_project/sram/input/rtl/mul_1.v
/home/ICer/NTT_project/sram/input/rtl/mul_2.v
/home/ICer/NTT_project/sram/input/rtl/mul_2_2.v
/home/ICer/NTT_project/sram/input/rtl/mul_2_top.v
/home/ICer/NTT_project/sram/input/rtl/stage_1.v
/home/ICer/NTT_project/sram/input/rtl/stage_2.v
/home/ICer/NTT_project/sram/input/rtl/stage_3.v
/home/ICer/NTT_project/sram/input/rtl/stage_4.v
/home/ICer/NTT_project/sram/input/rtl/stage_5.v
/home/ICer/NTT_project/sram/input/rtl/stage_6.v
/home/ICer/NTT_project/sram/input/rtl/stage_7.v
/home/ICer/NTT_project/sram/input/rtl/stage_8.v
/home/ICer/NTT_project/sram/input/rtl/switch.v
/home/ICer/NTT_project/sram/input/rtl/top.v
/home/ICer/NTT_project/sram/input/rtl/top_module.v
    }
   
    foreach rtl_file $rtl_files {
        echo "Analyzing: $rtl_file"
        analyze -format verilog -library WORK $rtl_file
    }

    # Elaborate 并检查
    elaborate ${top_module}
    if {[get_designs -quiet $top_module] == ""} {
        echo "Error: Elaborate failed for $top_module"
        exit 1
    }
    current_design $top_module

    # 综合流程
    set_svf ${top_module}.svf
   
    set status [link]
    if {!$status} {
        echo "Error: link failed"
        exit 1
    }

    # 约束和综合
    source /home/ICer/NTT_project/sram/input/tcl/Top_256.sdc
    check_timing

    # 报告
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/check_design_pre.rpt {check_design -nosplit}
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/check_timing_pre.rpt {check_timing}
   
    # 编译
    compile_ultra -no_autoungroup -no_seq_output_inversion

    # 后处理
    remove_unconnected_ports [find -hier cell "*"]
    change_name -rules verilog -hier
    set_svf -off

    # 最终报告
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/check_design_post.rpt {check_design -nosplit}
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/check_timing_post.rpt {check_timing}
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/area.rpt {report_area -nosplit -hier}
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/violators.rpt {report_constraints -nosplit -all_violators -significant_digits 4}
    redirect /home/ICer/NTT_project/sram/input/tcl/reports/timing.rpt {report_timing -nosplit -attributes -transition_time -max_path 5 -significant_digits 4}

    # 输出文件
    write -format verilog -hier -o mapped/${top_module}.v
    write -format ddc -hier -o mapped/${top_module}.ddc
    write_environment -format dctcl -environment_only -o mapped/${top_module}.tcl
    write_sdf mapped/${top_module}.sdf
    write_sdc -nosp mapped/${top_module}.sdc
}

lcy_cody

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