关于数字CLASS-D的经典文章

haiyanlan

xuexi…………ing

nkzz

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caosl

嗯,,不错的文章

hi_china59

Integrated stereo ΣΔ class D amplifier
Eric Gaalaas1, Bill Yang Liu2, Naoaki Nishimura2, Robert Adams1, Karl Sweetland1, and Rajeev Morajkar1
1 Analog Devices, Inc., digital audio group, Wilmington, MA, USA
2 Analog Devices, Inc., Japan design center, Tokyo, Japan
ABSTRACT
A 2x40W class D amplifier chip is realized in 0.6um BCDMOS technology, integrating 2 ΣΔ modulators and 2 Hbridge
power stages. Analog feedback from H-bridge outputs helps achieve 67 dB PSRR, 0.001% THD and 104 dB
dynamic range. The modulator clock rate is 6MHz, but dynamically adjusted quantizer hysteresis reduces output
data rate to 450kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output
spectrum contains a single peak, but is otherwise tone-free, unlike conventional PWM modulators which contain
energetic tones at harmonics of the PWM clock frequency.

hao-2

下了。学习。

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class d

chungming

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jiaopingmrs

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windows2007

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派大星

好的谢谢