Abstract
HV-BCDMOS-IC is a sort of complex circuit composed of Bipolar, CMOS and
LDMOS devices. In this paper, a 600V RESURF LDMOS with a p-type buried
layer and the metal field plate is proposed for improving the surface electric
field and reducing the on-resistance of LDMOS. A 600V BCD technology based
on standard Bi-CMOS process is realized by adding PN isolation, double well
and other optimized processes. With the process simulator TSUPREM-4 and 2-D
device simulator MEDICI, the processes and structures of different devices have
been simulated and optimized, especially for the HV-LDMOS. Using this
technology we developed a power IC. The test results show a good consistency
with that we have expected. The 600V BCD technology thus can be used in the
design of HVIC. |